参数资料
型号: LTC2435IGN#TRPBF
厂商: Linear Technology
文件页数: 14/42页
文件大小: 0K
描述: IC ADC DIFF I/REF 20BIT 16-SSOP
标准包装: 2,500
位数: 20
采样率(每秒): 15
数据接口: MICROWIRE?,串行,SPI?
转换器数目: 2
功率耗散(最大): 1mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-SSOP
包装: 带卷 (TR)
输入数目和类型: 1 个差分,双极
LTC2435/LTC2435-1
21
24351fc
For more information www.linear.com/LTC2435
applicaTions inForMaTion
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface.
The conversion result is shifted out of the device by an
externally generated serial clock (SCK) signal, see Figure
10. CS may be permanently tied to ground, simplifying
the user interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 2.2V. The level ap-
plied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.
Figure 10. External Serial Clock, CS = 0 Operation (2-Wire)
EOC
BIT 23
SDO
SCK
(EXTERNAL)
CS
MSB
LSB
SIG
BIT 0
BIT 5
BIT 19
BIT 18
BIT 20
BIT 21
BIT 22
DATA OUTPUT
CONVERSION
2435 F10
CONVERSION
VCC
FO
REF+
REF
SCK
IN+
IN
SDO
GND
CS
2
14
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
2-WIRE
INTERFACE
1
F
2.7V TO 5.5V
LTC2435/
LTC2435-1
= 50Hz REJECTION (LTC2435)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2435)
= 50Hz/60Hz REJECTION (LTC2435-1)
VCC
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
externalcontrollerindicatingtheconversionresultisready.
EOC = 1 while the conversion is in progress and EOC = 0
once the conversion is over. On the falling edge of EOC,
the conversion result is loaded into an internal static shift
register. Data is shifted out the SDO pin on each falling
edge of SCK enabling external circuitry to latch data on the
rising edge of SCK. EOC can be latched on the first rising
edge of SCK. On the 24th falling edge of SCK, SDO goes
HIGH (EOC = 1) indicating a new conversion has begun.
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