参数资料
| 型号： | LTC2442IG#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 7/32页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 4CH 36-SSOP |
| 标准包装： | 37 |
| 位数： | 24 |
| 采样率（每秒）： | 8k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 50mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 36-SSOP |
| 包装： | 管件 |
| 输入数目和类型： | 4 个单端，双极；2 个差分，双极 |
| 产品目录页面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC979A-ND - BOARD DELTA SIGMA ADC LTC2442 |
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LTC2442
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2442fa
For more information www.linear.com/LTC2442
selected speed/resolution and input channel is valid. This
is identical to the operation of the LTC2440 and LTC2444
through LTC2449.
While operating in the 2X mode, the device performs a
running average of the last two conversion results. This
automatically removes the offset and drift of the device
while increasing the output rate by 2X. The resolution
(noise) remains the same. If a new channel is selected,
the conversion result is valid for all conversions after
the first conversion (one cycle latency). If a new speed/
resolution is selected, the first conversion result is valid
but the resolution (noise) is a function of the running av-
erage. All subsequent conversion results are valid. If the
mode is changed from either 1X to 2X or 2X to 1X without
changing the resolution or channel, the first conversion
result is valid.
The 2X mode can also be used to increase the settling
time of the amplifier between readings. While operating in
the 2X mode, the multiplexer output (input to the buffer/
amplifier) is switched at the end of each conversion cycle.
Prior to concluding the data out/in cycle, the analog mul-
tiplexer output is switched. This occurs at the end of the
conversion cycle (just prior to the data output cycle) for
auto calibration. The time required to read the conversion
enables more settling time for the amplifier. The offset/
offset drift of the amplifier is automatically removed by
the converter’s auto calibration sequence for both the 1X
and 2X speed modes.
While operating in the 1X mode, if a new input channel
is selected the multiplexer is switched on the falling edge
of the 14th SCK (once the complete data input word is
programmed). The remaining data output sequence time
can be used to allow the external amplifier to settle.
BUSY
The BUSY output (Pin 2) is used to monitor the state of
conversion, data output and sleep cycle. While the part is
converting, the BUSY pin is HIGH. Once the conversion
is complete, BUSY goes LOW indicating the conversion is
complete and data out is ready. The part now enters the
sleep state. BUSY remains LOW while data is shifted out of
the device and SDI is shifted into the device. It goes HIGH
at the conclusion of the data input/output cycle indicating
a new conversion has begun. This rising edge may be used
to flag the completion of the data read cycle.
Serial Interface Timing Modes
The LTC2442’s 3- or 4-wire interface is SPI and MICROW-
IREcompatible.Thisinterfaceoffersseveralflexiblemodes
of operation. These include internal/external serial clock,
3- or 4-wire I/O, single cycle conversion and autostart. The
following sections describe each of these serial interface
timing modes in detail. In all these cases, the converter
can use the internal oscillator (FO = LOW) or an external
oscillator connected to the FO pin. Refer to Table 5 for a
summary.
Table 5. Interface Timing Modes
Configuration
SCK Source
Conversion Cycle Control
Data Output Control
Connection and Waveforms
External SCK, Single Cycle Conversion
External
CS and SCK
Figures 4, 5
External SCK, 2-Wire I/O
External
SCK
Figure 6
Internal SCK, Single Cycle Conversion
Internal
CS
↓
CS
↓
Figures 7, 8
Internal SCK, 2-Wire I/O, Continuous
Conversion
Internal
Continuous
Internal
Figure 9
applications inForMation
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