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参数资料
| 型号： | LTC2451CTS8B#TRMPBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO8 |
| 封装： | LEAD FREE, PLASTIC, MO-193, TSOT-23, 8 PIN |
| 文件页数： | 3/18页 |
| 文件大小： | 245K |
| 代理商： | LTC2451CTS8B#TRMPBF |
LTC2451
11
2451ff
GLOBAL ADDRESS
(1110111)
SLEEP
CONVERSION
S
W
ACK
WRITE (OPTIONAL)
P
2451 F09
DATA INPUT
Continuous Read/Write
Once the conversion cycle is concluded, the LTC2451 can
be written to, and then read from, using the Repeated Start
(Sr) command.
Figure 7 shows a cycle which begins with a data Write, a
Repeated Start, followed by a Read, and concluded with a
Stop command. The following conversion begins after all
16 bits are read out of the device, or after the Stop com-
mand, and uses the newly programmed conguration.
Discarding a Conversion Result and Initiating a New
Conversion with Optional Conguration Updating
At the conclusion of a conversion cycle, a Write cycle
can be initiated. Once the Write cycle is acknowledged, a
Stop (P) command initiates a new conversion. If a new
conguration is required, this data can be written into the
device and a Stop command initiates a new conversion
(see Figure 8).
Synchronizing the LTC2451 with the Global Address Call
The LTC2451 can also be synchronized with the global
address call (see Figure 9). To achieve this, the LTC2451
must rst have completed the conversion cycle. The
master issues a Start, followed by the LTC2451 global
address 1110111, and a Write request. The LTC2451 will
be selected and acknowledge the request. If desired, the
master then sends the Write byte to program the 30Hz
or 60Hz mode. After the optional Write byte, the master
ends the Write operation with a Stop. This will update
the conguration registers (if a Write byte was sent) and
initiate a new conversion on the LTC2451, as shown in
Figure 9. In order to synchronize the start of the conver-
sion without affecting the conguration registers, the
Write operation can be aborted with a Stop. This initiates
a new conversion on the LTC2451 without changing the
conguration registers.
PRESERVING THE CONVERTER ACCURACY
The LTC2451 is designed to dramatically reduce the conver-
sion result’s sensitivity to device decoupling, PCB layout,
antialiasing circuits, line and frequency perturbations. Nev-
ertheless, in order to preserve the high accuracy capability
of this part, some simple precautions are desirable.
Digital Signal Levels
Due to the nature of CMOS logic, it is advisable to keep
input digital signals near GND or VCC. Voltages in the
Figure 7. Write, Read, Start Conversion
Figure 8. Start a New Conversion without Reading Old Conversion Result
APPLICATIONS INFORMATION
Figure 9. Synchronize the LTC2451 with the Global Address Call
Figure 6. Consecutive Reading at the Same Conguration
SLEEP
7-BIT ADDRESS
(0010100)
SP
P
R
ACK
READ
DATA OUTPUT
CONVERSION
2451 F06
SLEEP
7-BIT ADDRESS
(0010100)
SP
R
ACK
READ
DATAOUTPUT
CONVERSION
SLEEP
7-BIT ADDRESS
(0010100)
7-BIT ADDRESS
(0010100)
S
R
Sr
W ACK
WRITE
DATA OUTPUT
DATA INPUT
ADDRESS
CONVERSION
2451 F05
P
ACK
READ
SLEEP
7-BIT ADDRESS
(0010100)
WRITE
(OPTIONAL)
SP
W ACK
DATA INPUT
CONVERSION
2451 F08
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