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| 型号： | LTC2496CUHF#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 14/32页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT DELTA SIG 38-QFN |
| 标准包装： | 52 |
| 位数： | 16 |
| 采样率（每秒）： | 6.9 |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 800µW |
| 电压电源： | 单电源 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-WFQFN 裸露焊盘 |
| 供应商设备封装： | 38-QFN（5x7） |
| 包装： | 管件 |
| 输入数目和类型： | 16 个单端，双极；8 个差分，双极 |
| 产品目录页面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC1011A-B-ND - BOARD DELTA SIGMA ADC LTC2496 |
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LTC2496
2496fb
applicaTions inForMaTion
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH any time between the 1st rising edge and the 24th
falling edge of SCK, see Figure 8. On the rising edge of CS,
the device aborts the data output state and immediately
initiates a new conversion.In order to program a new input
channel,8SCKclockpulsesarerequired.Ifthedataoutput
sequence is aborted prior to the 8th falling edge of SCK,
the new input data is ignored and the previously selected
input channel remains valid. If the rising edge of CS occurs
after the 8th falling edge of SCK, the new input channel is
loaded and valid for the next conversion cycle.
Internal Serial Clock, 3-Wire I/O, Continuous
Conversion
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated
serial clock (SCK) signal, see Figure 9. In this case, CS is
permanently tied to ground, simplifying the user interface
or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 4ms after VCC exceeds 2V. An internal weak
pull-upisactiveduringthePORcycle;therefore,theinternal
serial clock timing mode is automatically selected if SCK
is floating or driven HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating
the conversion has finished and the device has entered
the sleep state. The device remains in the sleep state a
minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting and inputting data.
The input data is shifted through the SDI pin on the ris-
ing edge of SCK (including the first rising edge) and the
output data is shifted out the SDO pin on the falling edge
of SCK. The data input/output cycle is concluded and a
new conversion automatically begins after the 24th rising
edge of SCK. During the next conversion, SCK and SDO
remain HIGH until the conversion is complete.
Figure 8. Internal Serial Clock, Reduced Data Output Length with Valid Channel Selection
10F
0.1F
2.7V TO 5.5V
Hi-Z
2496 F08
CS
SCK
(INTERNAL)
SDI
SDO
CONVERSION
SLEEP
DATA INPUT/OUTPUT
CONVERSION
VCC
fO
REF+
REF–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28
35
29
30
8
15
16
23
7
38
37
1,3,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2496
4-WIRE
SPI INTERFACE
EOC
BIT 14 BIT 13
1
2
3
4
5
6
7
8
9
10
1
0
EN
SGL
A2
A1
A0
ODD
DON'T CARE
MSB
SIG
“0”
OPTIONAL
10k
VCC
<tEOCTEST
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15
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