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参数资料
| 型号： | LTC2497IUHF#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 2/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT W/PGA 38-QFN |
| 标准包装： | 52 |
| 位数： | 16 |
| 采样率（每秒）： | 7.5 |
| 数据接口： | I²C，串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 480µW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-WFQFN 裸露焊盘 |
| 供应商设备封装： | 38-QFN（5x7） |
| 包装： | 管件 |
| 输入数目和类型： | 16 个单端，双极；8 个差分，双极 |
| 配用： | DC1012A-B-ND - BOARD DELTA SIGMA ADC LTC2497 |
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LTC2497
0
2497fa
CONVERTER OPERATION
Converter Operation Cycle
The LTC2497 is a multichannel, low power, delta-sigma
analog-to-digital converter with a 2-wire, I2C interface.
Its operation is made up of four states (see Figure 1).
The converter operating cycle begins with the conver-
sion, followed by the sleep state and ends with the data
input/output cycle.
applicaTions inForMaTion
Figure 1. State Transition Table
CONVERSION
SLEEP
2497 F01
YES
NO
ACKNOWLEDGE
YES
NO
STOP
OR READ
24 BITS
DATA OUTPUT/INPUT
POWER-ON RESET
DEFAULT INPUT CHANNEL:
IN+ = CH0, IN– = CH1
The device will not acknowledge an external request dur-
ing the conversion state. After a conversion is finished,
the device is ready to accept a read/write request. Once
the LTC2497 is addressed for a read operation, the device
begins outputting the conversion result under the control
of the serial clock (SCL). There is no latency in the conver-
sion result. The data output is 24 bits long and contains a
16-bit plus sign conversion result. Data is updated on the
falling edges of SCL allowing the user to reliably latch data
on the rising edge of SCL. A new conversion is initiated
by a stop condition following a valid write operation or an
incomplete read operation. The conversion automatically
begins at the conclusion of a complete read cycle (all 24
bits read out of the device).
Ease of Use
The LTC2497 data output has no latency, filter settling
delay, or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multipleanaloginputsisstraightforward.Eachconversion,
immediately following a newly selected input is valid and
accurate to the full specifications of the device.
The LTC2497 automatically performs offset and full-scale
calibration every conversion cycle independent of the
input channel selected. This calibration is transparent
to the user and has no effect on the operation cycle de-
scribed above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage variation, input channel,
and temperature drift.
Easy Drive Input Current Cancellation
The LTC2497 combines a high precision, delta-sigma ADC
with an automatic, differential, input current cancellation
frontend.Aproprietaryfrontendpassivesamplingnetwork
transparently removes the differential input current. This
enables external RC networks and high impedance sen-
sors to directly interface to the LTC2497 without external
amplifiers. The remaining common mode input current
is eliminated by either balancing the differential input im-
pedances or setting the common mode input equal to the
Initially, at power-up, the LTC2497 performs a conver-
sion. Once the conversion is complete, the device enters
the sleep state. In the sleep state, power consumption is
reduced by two orders of magnitude. The part remains in
the sleep state as long it is not addressed for a read/write
operation. The conversion result is held indefinitely in a
static shift register while the part is in the sleep state.
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