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参数资料
| 型号： | LTC2620IUFD#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 7 us SETTLING TIME, 12-BIT DAC, PQCC20 |
| 封装： | 4 X 5 MM, LEAD FREE, PLASTIC, MO-220, QFN-20 |
| 文件页数： | 7/20页 |
| 文件大小： | 338K |
| 代理商： | LTC2620IUFD#PBF |
LTC2600/LTC2610/LTC2620
15
2600fe
The GND pin functions both as the node to which the refer-
ence and output voltages are referred and as a return path
for power currents in the device. Because of this, careful
thought should be given to the grounding scheme and
board layout in order to ensure rated performance.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
The GND pin of the part should be connected to analog
ground. Resistance from the GND pin to system star
ground should be as low as possible. Resistance here will
add directly to the effective DC output impedance of the
device (typically 0.025Ω), and will degrade DC crosstalk.
Note that the LTC2600/LTC2610/LTC2620 are no more
susceptible to these effects than other parts of their type;
on the contrary, they allow layout-based performance
improvements to shine rather than limiting attainable
performance with excessive internal resistance.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited
to voltages within the supply range.
Since the analog outputs of the device cannot go below
ground, they may limit for the lowest codes as shown
in Figure 3b. Similarly, limiting can occur near full scale
when the REF pin is tied to VCC. If VREF = VCC and the DAC
full-scale error (FSE) is positive, the output for the highest
codes limits at VCC as shown in Figure 3c. No full-scale
limiting can occur if VREF is less than VCC – FSE.
Offset and linearity are dened and tested over the region
of the DAC transfer function where no output limiting can
occur.
OPERATION
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| LTC2610IUFD#TRPBF | SERIAL INPUT LOADING, 9 us SETTLING TIME, 14-BIT DAC, PQCC20 |
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