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参数资料
| 型号： | LTC2910HDHC#TR |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 电源管理 |
| 英文描述： | 8-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
| 封装： | 5 X 3 MM, PLASTIC, MO-229WJED-1, DFN-16 |
| 文件页数： | 2/16页 |
| 文件大小： | 520K |
| 代理商： | LTC2910HDHC#TR |
LTC2910
10
2910fc
voltages fell below the exact threshold for a specied mar-
gin. All LTC2910 inputs have a relative threshold accuracy
of ±1.5% over the full operating temperature range.
For example, when the LTC2910 is programmed to moni-
tor a 5V input with a 10% tolerance, the desired UV trip
point is 4.5V. Because of the ±1.5% relative accuracy of
the LTC2910, the UV trip point is between 4.433V and
4.567V which is 4.5V ±1.5%.
The accuracy of the resistances chosen for RA and RB affect
the UV trip point as well. Using the example just given,
if the resistances used to set the UV trip point have 1%
accuracy, the UV trip range is between 4.354V and 4.650V.
This is illustrated in the following calculations.
The UV trip point is given as
VUV = 0.5V 1+
RB
RA
The two extreme conditions, with a relative accuracy of
1.5% and resistance accuracy of 1%, result in
VUV(MIN) = 0.5V 0.985 1+
RB 0.99
RA 1.01
and
VUV(MAX) = 0.5V 1.015 1+
RB 1.01
RA 0.99
For a desired trip point of 4.5V,
RB
RA
= 8
Therefore,
VUV(MIN) = 0.5V 0.985 1+ 8
0.99
1.01
= 4.354V
and
VUV(MAX) = 0.5V 1.015 1+ 8
1.01
0.99
= 4.650V
Glitch Immunity
In any supervisory application, noise riding on the moni-
tored DC voltage causes spurious resets. To solve this
problem without adding hysteresis, which causes a new
error term in the trip voltage, the LTC2910 lowpass lters
the output of the rst stage comparator at each input.
This lter integrates the output of the comparator before
asserting the reset output logic. A transient at the input
of the comparator of sufcient magnitude and duration
triggers the output logic. The Typical Performance Char-
acteristics section shows a graph of the Transient Duration
vs. Comparator Overdrive.
RST/RST Timing
The LTC2910 has an adjustable timeout period (tRST) that
holds RST and RST asserted after all faults have cleared.
This assures a minimum reset pulse width allowing a
settling time delay for the monitored voltage after it has
entered the valid region of operation.
When any input drops below its designed threshold, the
RST pin asserts low and the RST pin asserts high. When
all inputs recover above their designed thresholds, the
reset delay timer starts. If all inputs remain above their
designed thresholds when the timer nishes, the RST
pin weakly pulls high and the RST pin strongly pulls low.
However, if any input falls below its designed threshold
during this timeout period, the timer resets and restarts
when all inputs are above the designed thresholds.
Selecting the Reset Timing Capacitor
The reset timeout period (tRST) for the LTC2910 is adjust-
able to accommodate a variety of applications. Connecting
a capacitor, CTMR, between the TMR pin and ground sets
the timeout period. The value of capacitor needed for a
particular timeout period is:
CTMR = tRST 115 10–9 (F/s)
The Reset Timeout Period vs. Capacitance graph found
in the Typical Performance Characteristics section shows
APPLICATIONS INFORMATION
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