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参数资料
| 型号： | LTC2919HDDB-5#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO10 |
| 封装： | 3 X 2 MM, LEAD FREE, PLASTIC, MO-229WECD-1, DFN-10 |
| 文件页数： | 5/16页 |
| 文件大小： | 195K |
| 代理商： | LTC2919HDDB-5#PBF |
LTC2919
13
2919f
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If the user wishes to avoid having an external capacitor,
the TMR pin should be tied to ground, switching the part
to an internal 200ms timer.
If the user requires a shorter timeout than 400μs, or
wishes to perform application-specic processing of the
reset output, the part may be put in comparator mode by
tying the TMR pin to VCC. In comparator mode, the timer
is bypassed and comparator outputs go straight to the
reset output.
The current required to hold TMR at ground or VCC is
about 2.2μA. To force the pin from the oating state to
ground or VCC may require as much as 100μA during the
transition.
When the part is in comparator mode, one of the two
means of preventing false reset has been removed, so
a small amount of one-sided hysteresis is added to the
inputs to prevent oscillation as the monitored voltage
passes through the threshold. This hysteresis is such
that the valid-to-invalid transition threshold is unchanged,
but the invalid-to-valid threshold is moved by about
0.7%. Thus, when the ADJ input polarity is positive,
the threshold voltage is 500mV nominal when the in-
put is above 500mV. As soon as the input drops below
500mV, the threshold moves up to 503.5mV nominal.
Conversely, when congured as a negative-polarity input,
the threshold is 500mV when the input is below 500mV,
and switches to 496.5mV when the input goes above
500mV.
The comparator mode feature is enabled by directly short-
ing the TMR pin to the VCC pin. Connecting the pin to any
other voltage may have unpredictable results.
Selecting the Reset Timing Capacitor
Connecting a capacitor, CTMR, between the TMR pin and
ground sets the reset timeout, tRST. The following formula
approximates the value of capacitor needed for a particular
timeout:
CTMR = tRST 110 [pF/ms]
Leaving the TMR pin open with no external capacitor
generates a reset timeout of approximately 400μs.
Maximum length of the reset timeout is limited by the
ability of the part to charge a large capacitor on start-up.
Initially, with a large (discharged) capacitor on the TMR
pin, the part will assume it is in internal timer mode (since
the pin voltage will be at ground). If the 2.2μA owing
out of the TMR pin does not charge the capacitor to the
ground-sense threshold within the rst 200ms after sup-
plies become good, the internal timer cycle will complete
and RST will go high too soon.
This imposes a practical limit of 1μF (9 second timeout) if
the length of timeout during power-up needs to be longer
than 200ms. If the power-up timeout is not important,
larger capacitors may be used, subject to the limitation
that the capacitor leakage current must not exceed 500nA,
or the function of the timer will be impaired.
Output Pins Characteristics
The DC characteristics of the OUT1, OUT2 and RST pull-
down strength are shown in the Typical Performance
Characteristics section. OUT1, OUT2 and RST are open-
drain pins and thus require external pull-up resistors to
the logic supply. They may be pulled above VCC, providing
the absolute maximum rating of the pin are observed.
As noted in the discussion of power up and power down,
the circuits that drive OUT1, OUT2 and RST are powered
by VCC. During a fault condition, VCC of at least 0.5V
guarantees a VOL of 0.15V.
The open-drain nature of the RST pin allows for wired-OR
connection of several LTC2919s to monitor more than two
supplies (see Typical Applications). Other logic with open-
drain outputs may also connect to the RST line, allowing
other logic-determined conditions to issue a reset.
APPLICATIO S I FOR ATIO
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