- 您现在的位置：买卖IC网 > PDF目录15323 > LTC2928CUHF#TRPBF (Linear Technology)IC PWR SUPPLY SEQUENCER 38-QFN PDF资料下载
参数资料
| 型号： | LTC2928CUHF#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 24/32页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUPPLY SEQUENCER 38-QFN |
| 标准包装： | 2,500 |
| 类型： | 序列发生器 |
| 监视电压数目： | 4 |
| 复位： | 低有效 |
| 复位超时： | 最小为 5 ms |
| 电压 - 阀值： | 可调节/可选择 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-WFQFN 裸露焊盘 |
| 供应商设备封装： | 38-QFN（5x7） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页当前第24页第25页第26页第27页第28页第29页第30页第31页第32页
LTC2928
APPLICATIO S I FOR ATIO
C STMR ( F ) = STMR
C STMR =
= 3300 pF
LTC2928DesignExample
The following design example describes a power supply se-
quencing application using many features of the LTC2928.
The example discusses a configuration procedure for the
LTC2928 in a system containing a dual-supply DSP and
FPGA. The design example schematic is shown in Figure
20. The three main operating phases—sequence-up,
supply monitor, and sequence-down are discussed. All
resistor, capacitor and configuration settings are reviewed.
A timing diagram for sequencing-up is shown in Figure
18 and sequencing-down in Figure 19.
A main 3.3V supply provides application power, including
V CC for the LTC2928, and is sub-regulated to provide the
lower voltages (2.5V, 1.8V, 1.5V). The LTC2928 controls
external N-channel MOSFETs connected to two of the four
supplies, used to pass power to the loads. The DSP core
is powered from 1.8V and its I/O uses the 3.3V supply.
The FPGA internals are powered from 1.5V and its I/O
uses 2.5V.
1) Configure the LTC2928 based on application
requirements
a. Apply device power.
Since the HV CC input is unused, connect it to ground.
Connect the main 3.3V supply to the V CC pin. Bypass
V CC with 0.1 μ F to ground.
b. Monitored Supply Polarity
The application monitors four positive voltages. Connect
the voltage selection input (VSEL) to ground (Table 1).
c. Device designations
The application requires only one LTC2928, and it is con-
sidered the MASTER device. By definition, it is also the
FIRST and LAST device. Configure the MASTER/FIRST
designation with the three-state MS1 and MS2 inputs
connected to ground (Table 2). With MS1 and MS2 at
ground, a reset fault is generated if RST pulls low during
the supply monitor phase. Configure LAST device status
with a 3.32k resistor from DONE to V CC .
d. Sequence threshold selection
During the sequencing-up or sequencing-down phase,
time positions terminate (CAS is released) when a supply
(or supplies) reaches it sequence threshold. This design
example requires sequence thresholds at 67% of their
under-voltage threshold. Therefore, connect SQT1 to GND
and SQT2 to V CC (Table 4).
e. Choose minimum power supply enable spacing
The shortest time between successive power supply
enables (t CAS(HI) ) is controlled by a capacitor connected
to the STMR pin and ground (also referenced as the se-
quence timer period, t STMR ). The sequence timer period
for this application is 29ms. Calculate the sequence timer
capacitor from
t (s)
8 . 67 M ?
For this application,
29 ms
8 . 67 M ?
f. Supply order (time position)
The application requires the 1.8V DSP core supply to start
first, about 100ms after the ON signal is received. The 1.8V
supply is monitored on the V3 input and implies selection
of the RT3 resistor, since monitor inputs correspond nu-
merically with the RT and EN inputs. The 100ms required
delay is approximately three sequence timer periods, so
configure the first supply for time position 3 (select RT3
= 24.3k). Table 3 shows the recommended RT resistor
values as a function of time position.
The 3.3V DSP I/O supply (monitored on V4) needs to turn
on just after the core supply is alive, in order to minimize
electrical stress and the possibility of bus contention. Turn
on pass transistor N4 approximately 29ms after the core
supply reaches its sequence threshold by selecting time
position 4 (RT4 = 15k).
The FPGA needs to be powered about 100ms after the
DSP, with its core and I/O supplies enabled simultane-
ously. The 2.5V I/O supply is monitored on V1, and the
1.5V core supply is monitored on V2. Since the required
turn on delay is about three sequence timer periods after
the DSP, select RT1 = RT2 = 3.4k (time position 7).
2928f
24
相关PDF资料 |
PDF描述 |
|---|---|
| UPM1E122MHD | CAP ALUM 1200UF 25V 20% RADIAL |
| RMC18DREF | CONN EDGECARD 36POS .100 EYELET |
| ADM8695ARWZ | IC SUPERVSR MPU 4.65V ADJ 16SOIC |
| LTC2913CMS-2#PBF | IC VOLT MONITOR DUAL 10-MSOP |
| MIC2184YQS TR | IC REG CTRLR BUCK PWM CM 16-QSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2928IG | 制造商:Linear Technology 功能描述:Volt Supervisor Sequencer 36-Pin SSOP |
| LTC2928IG#PBF | 功能描述:IC PWR SUPPLY SEQUENCER 36SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 其它有关文件:STM6905 View All Specifications 标准包装:1 系列:- 类型:多压监控器 监视电压数目:5 输出:开路漏极或开路集电极 复位:低有效 复位超时:最小为 140 ms 电压 - 阀值:2.188V，2.955V，可调，可调，可调 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 供应商设备封装:8-TSSOP 包装:Digi-Reel® 产品目录页面:1197 (CN2011-ZH PDF) 其它名称:497-8728-6 |
| LTC2928IG#TRPBF | 功能描述:IC PWR SUPPLY SEQUENCER 36SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 标准包装:1 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:开路漏极或开路集电极 复位:高有效 复位超时:- 电压 - 阀值:1.8V 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:6-TSOP（0.059"，1.50mm 宽）5 引线 供应商设备封装:5-TSOP 包装:剪切带 (CT) 其它名称:NCP301HSN18T1GOSCT |
| LTC2928IUHF | 制造商:Linear Technology 功能描述:Volt Supervisor Sequencer 38-Pin QFN EP |
| LTC2928IUHF#PBF | 功能描述:IC PWR SUPPLY SEQUENCER 38-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 其它有关文件:STM6905 View All Specifications 标准包装:1 系列:- 类型:多压监控器 监视电压数目:5 输出:开路漏极或开路集电极 复位:低有效 复位超时:最小为 140 ms 电压 - 阀值:2.188V，2.955V，可调，可调，可调 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 供应商设备封装:8-TSSOP 包装:Digi-Reel® 产品目录页面:1197 (CN2011-ZH PDF) 其它名称:497-8728-6 |
发布紧急采购，3分钟左右您将得到回复。