参数资料
| 型号： | LTC3025IDC#TRMPBF |
| 厂商： | Linear Technology |
| 文件页数： | 7/12页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ .3A 6-DFN |
| 产品培训模块： | More Information on LDOs |
| 标准包装： | 500 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 0.4 V ~ 3.6 V |
| 输入电压： | 0.9 V ~ 5.5 V |
| 电压 - 压降（标准）： | 0.045V @ 300mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 300mA（最小） |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-WFDFN 裸露焊盘 |
| 供应商设备封装： | 6-DFN-EP（2x2） |
| 包装： | 带卷 (TR) |
LTC3025
APPLICATIONS INFORMATION
using the formula in Figure 2. Note that in shutdown the
output is turned off and the divider current will be zero
once C OUT is discharged.
The LTC3025 operates at a relatively high gain of –0.7μV/
mA referred to the ADJ input. Thus a load current change
of 1mA to 300mA produces a –0.2mV drop at the ADJ
input. To calculate the change referred to the output sim-
ply multiply by the gain of the feedback network (i. e. ,1
+ R2/R1). For example, to program the output for 1.2V
choose R2/R1 = 2. In this example, an output current
change of 1mA to 300mA produces –0.2mV ? (1 + 2) =
0.6mV drop at the output.
Because the ADJ pin is relatively high impedance (depend-
ing on the resistor divider used) , stray capacitance at this
pin should be minimized (<10pF) to prevent phase shift
increase the effective output capacitor value. High ESR
tantalum and electrolytic capacitors may be used, but
a low ESR ceramic capacitor must be in parallel at the
output. There is no minimum ESR or maximum capacitor
size requirements.
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common di-
electrics used are Z5U, Y5V, X5R and X7R. The Z5U and
Y5V dielectrics are good for providing high capacitances
in a small package, but exhibit large voltage and tem-
perature coef?cients as shown in Figures 3 and 4. When
used with a 2V regulator, a 1μF Y5V capacitor can lose as
much as 75% of its initial capacitance over the operating
in the error ampli?er loop. Additionally, special attention
should be given to any stray capacitances that can couple
external signals onto the ADJ pin producing undesirable
output ripple. For optimum performance connect the ADJ
pin to R1 and R2 with a short PCB trace and minimize all
other stray capacitance to the ADJ pin.
20
0
–20
–40
–60
BOTH CAPACITORS ARE 1μF,
10V, 0603 CASE SIZE
X5R
Y5V
( )
V OUT = 0.4V 1
OUT
R2
R2
R1
–80
ADJ
R1
C OUT
–100
0
2
4 6
DC BIAS VOLTAGE (V)
8
10
GND
3025 F03
3025 F02
Figure 3. Ceramic Capacitor DC Bias Characteristics
Figure 2. Programming the LTC3025
20
Output Capacitance and Transient Response
0
The LTC3025 is designed to be stable with a wide range of
ceramic output capacitors. The ESR of the output capaci-
tor affects stability, most notably with small capacitors. A
minimum output capacitor of 1μF with an ESR of 0.05Ω
or less is recommended to ensure stability. The LTC3025
is a micropower device and output transient response
–20
–40
–60
–80
Y5V
X5R
will be a function of output capacitance. Larger values
of output capacitance decrease the peak deviations and
BOTH CAPACITORS ARE 1μF,
10V, 0603 CASE SIZE
–100
–50 –25 0 25 50
75
provide improved transient response for larger load current
changes. Note that bypass capacitors used to decouple
individual components powered by the LTC3025 will
TEMPERATURE (°C)
3025 F04
Figure 4. Ceramic Capacitor Temperature Characteristics
3025fd
7
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相关代理商/技术参数 |
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| LTC3025IDC-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:300mA Micropower VLDO Linear Regulator |
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| LTC3026EDD | 制造商:Linear Technology 功能描述:LDO Regulator Pos 0.4V to 2.6V 1.5A 10-Pin DFN EP |
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