参数资料
型号: LTC3026EMSE#TRPBF
厂商: Linear Technology
文件页数: 7/18页
文件大小: 0K
描述: IC REG LDO ADJ 1.5A 10-MSOP
产品培训模块: More Information on LDOs
标准包装: 2,500
稳压器拓扑结构: 正,可调式
输出电压: 0.4 V ~ 2.6 V
输入电压: 1.14 V ~ 5.5 V
电压 - 压降(标准): 0.1V @ 1.5A
稳压器数量: 1
电流 - 输出: 1.5A(最小)
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)裸露焊盘
供应商设备封装: 10-MSOP 裸露焊盘
包装: 带卷 (TR)
LTC3026
PIN FUNCTIONS
IN (Pins 1, 2): Input Supply Voltage. Output load current
is supplied directly from IN. The IN pin should be locally
bypassed to ground if the LTC3026 is more than a few
inches away from another source of bulk capacitance.
In general, the output impedance of a battery rises with
frequency, so it is usually advisable to include an input
bypass capacitor when supplying IN from a battery. A
capacitor in the range of 0.1μF to 4.7μF is usually sufficient.
GND (Pin 3, Exposed Pad Pin 11): Ground and Heat Sink.
Connect the exposed pad to the PCB ground plane or large
pad for optimum thermal performance.
SW (Pin 4): Boost Switching Pin. This is the boost converter
switching pin. A 4.7μH to 40μH inductor able to handle a
peak current of 150mA is connected from this pin to V IN .
The boost converter can be disabled by floating this pin.
This allows the use of an external boosted supply from
a second LTC3026 or other source. See Operating with
Boost Converter Disabled section for more information.
BST (Pin 5): Boost Output Voltage Pin. With boost con-
verter enabled bypass the BST pin with a ≥4.7μF low ESR
ceramic capacitor to GND (C BST ). BST does not load V IN
when in shutdown, but is diode connected to IN through
the external inductor, thus, will not go to ground with V IN
present. Users should not present any loads to the BST
pin (with boost enabled) until PG signals that regulation
has been achieved. When providing an external BST volt-
age (i.e. boost converter disabled) a 1μF low ESR ceramic
capacitor can be used.
SHDN (Pin 6): Shutdown Input Pin, Active Low. This pin
is used to put the LTC3026 into shutdown. The SHDN pin
current is typically less than 10nA. The SHDN pin cannot
be left floating and must be tied to a valid logic level (such
as IN) if not used.
PG (Pin 7): Power Good Pin. When PG is high impedance
OUT is in regulation, and low impedance when OUT is in
shutdown or out of regulation.
ADJ (Pin 8): Output Adjust Pin. This is the input to the error
amplifier. It has a typical bias current of 0.1nA flowing into
the pin. The ADJ pin reference voltage is 0.4V referenced
to ground. The output voltage range is 0.4V to 2.6V and is
typically set by connecting ADJ to a resistor divider from
OUT to GND. See Figure 2.
OUT (Pins 9, 10): Regulated Output Voltage. The OUT pins
supply power to the load. A minimum output capacitance
of 5μF is required to ensure stability. Larger output capaci-
tors may be required for applications with large transient
loads to limit peak voltage transients. See the Applica-
tions Information section for more information on output
capacitance.
3026ff
7
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