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参数资料
| 型号： | LTC3104IDE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 8/20页 |
| 文件大小： | 339K |
| 描述： | IC REG DL BUCK/LINEAR SYNC 14DFN |
| 标准包装： | 91 |
| 拓扑： | 降压（降压）同步（1），线性（LDO）（1） |
| 功能： | 任何功能 |
| 输出数： | 2 |
| 频率 - 开关： | 1.2MHz |
| 电压/电流 - 输出 1： | 0.6 V ~ 13.8 V，300mA |
| 电压/电流 - 输出 2： | 0.6 V ~ 14.5 V，10mA |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 无 |
| 电源电压： | 2.5 V ~ 15 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-WFDFN 裸露焊盘 |
| 供应商设备封装： | 14-DFN（4x3） |
| 包装： | 管件 |
LTC3104
8
3104f
PIN FUNCTIONS (DFN/MSOP)
MODE (Pin 1/Pin 2): Logic-Controlled Input to Select
Mode of Operation. Forcing this pin high commands high
efficiency automatic Burst Mode operation where the buck
will automatically transition from PWM operation at heavy
load to Burst Mode operation at light loads. Forcing this
pin low commands low noise, fixed frequency, forced
continuous operation.
V
IN
(Pin 2/Pin 3): Main Supply Pin. Decouple with a 10?/SPAN>F
or larger ceramic capacitor. The capacitor should be as
close to the part as possible.
SW (Pin 3/Pin 4): Switch Pin Connects to the Inductor.
This pin connects to the drains of the internal main and
synchronous power MOSFET switches.
BST (Pin 4/Pin 5): Bootstrapped Floating Supply for High
Side Gate Drive. Connect to SW through a 22nF (minimum)
capacitor. The capacitor must be connected between BST
and SW and be located as close as possible to the part
as possible.
GND (Pin 5/Pin 6): Power Ground.
RUNLDO (Pin 6/Pin 7): Logic-Controlled LDO Enable Pin.
This pin may be tied to V
IN
to enable the LDO.
PGOOD (Pin 7/Pin 8): Open-drain output that is pulled
to ground when the feedback voltage falls 10% (typical)
below the regulation point, during a thermal shutdown
event or if the converter is disabled. The PGOOD output
is valid 1ms after the buck converter is enabled.
NC (Pin 8/Pins 1, 9, 16): No Connect Pin(s) Must Be Tied
to GND.
V
CC
(Pin 9/Pin 10): Internally Regulated Supply Rail.
Internal power rail regulated off of V
IN
to power control
circuitry. Decouple with a 1礔 or larger ceramic capacitor
placed as close to the part as possible.
RUN (Pin 10/Pin 11): Run Pin Comparator Input. A voltage
greater than 0.84V will enable the IC. Tie this pin to V
IN
to
enable the IC or connect to an external resistor divider from
V
IN
to provide an accurate undervoltage lockout threshold.
60mV of hysteresis is provided internally.
FB (Pin 11/Pin 12): Feedback Input to Error Amplifier.
The resistor divider connected to this pin sets the buck
converter output voltage.
FBLDO (Pin 12/Pin 13): Feedback Input to the LDO Error
Amplifier. The resistor divider on this pin sets the LDO
output voltage.
V
LDO
(Pin 13/Pin 14): LDO Regulator Output. Decouple
with a 4.7礔 or larger ceramic capacitor placed as close
to the part as possible.
V
INLDO
(Pin 14/Pin 15): LDO Supply Pin (15V Maximum).
Decouple with a 10礔 or larger ceramic capacitor.
GND (Exposed Pad Pin 15/Exposed Pad Pin 17): Back-
pad Ground Common. This pad must be soldered to the
PC board and connected to the ground plane for optimal
thermal performance.
TYPICAL PERFORMANCE CHARACTERISTICS T
A
= 25癈 unless otherwise noted
LDO Output Voltage
Load Step
LDO Ripple Rejection
(Automatic Burst Mode Operation)
V
LDO
20mV/DIV
AC-COUPLED
I
LOAD
10mA/DIV
20ms/DIV
3104 G31
I
LOAD
= LOAD STEP, NO LOAD TO 10mA
V
LDO
= 1.8V
V
IN(LDO)
= V
IN
= 10V
C
IN
= 10礔
C
OUT
= 10礔
V
LDO
20mV/DIV
AC-COUPLED
V
OUT
50mV/DIV
AC-COUPLED
I
L
200mA/DIV
50祍/DIV
3104 G32
I
LOAD
= 10mA
I
LDO
= 1mA
V
LDO
= 1.8V, V
IN
= 10V
V
IN(LDO)
= V
OUT
= 2.5V
C
IN
= 10礔, C
OUT
= 22礔
C
LDO
= 4.7礔, L = 10礖
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