参数资料
型号: LTC3214EDD#TRPBF
厂商: Linear Technology
文件页数: 9/12页
文件大小: 0K
描述: IC LED DRIVR WHITE BCKLGT 10-DFN
标准包装: 2,500
拓扑: 升压(升压),切换式电容器(充电泵)
输出数: 1
内部驱动器:
类型 - 主要: 闪灯/白光
类型 - 次要: 白色 LED
频率: 600kHz ~ 1.2MHz
电源电压: 2.9 V ~ 4.5 V
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘
供应商设备封装: 10-DFN(3x3)
包装: 带卷 (TR)
工作温度: -40°C ~ 85°C
LTC3214
APPLICATIONS INFORMATION
ceramic capacitor in a 0603 case may not provide any more
capacitance than a 0.22μF, 10V, X7R available in the same
case. The capacitor manufacturer’s data sheet should be
consulted to determine what value of capacitor is needed
to ensure minimum capacitances at all temperatures and
voltages.
Table 1 shows a list of ceramic capacitor manufacturers
and how to contact them.
Table 1. Recommended Capacitor Vendors
Magnetic ?elds can also be generated if the ?ying capacitors
are not close to the LTC3214 (i.e., the loop area is large).
To decouple capacitive energy transfer, a Faraday shield
may be used. This is a grounded PCB trace between the
sensitive node and the LTC3214 pins. For a high quality
AC ground, it should be returned to a solid ground plane
that extends all the way to the LTC3214.
The following guidelines should be followed when design-
ing a PCB layout for the LTC3214.
AVX
Kemet
Murata
Taiyo Yuden
Vishay
TDK
www.avxcorp.com
www.kemet.com
www.murata.com
www.t-yuden.com
www.vishay.com
www.tdk.com
? The Exposed Pad should be soldered to a large copper
plane that is connected to a solid, low impedance ground
plane using plated, through-hole vias for proper heat
sinking and noise protection.
? Input and output capacitors (C IN and C CPO ) must also
be placed as close to the part as possible.
Layout Considerations and Noise
Due to the high switching frequency and the transient
currents produced by the LTC3214, careful board layout
is necessary. A true ground plane and short connections
to all capacitors will improve performance and ensure
proper regulation under all conditions. An example of
such a layout is shown in Figure 4.
The ?ying capacitor pins C1 + , C2 + , C1 – and C2 – will have
very high edge rate waveforms. The large dv/dt on these
pins can couple energy capacitively to adjacent PCB runs.
? The ?ying capacitors must also be placed as close to
the part as possible. The traces running from the pins
to the capacitor pads should be as wide as possible.
? V IN , CPO and I LED traces must be made as wide as
possible. This is necessary to minimize inductance,
as well as provide suf?cient area for high current
applications.
? LED pads must be large and should be connected to
as much solid metal as possible to ensure proper heat
sinking.
C1
C CPO
PIN 1
C2
C IN
3214 F04
Figure 4. Example Board Layout
3214fb
9
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