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参数资料
| 型号： | LTC3221EDC#TRMPBF |
| 厂商： | Linear Technology |
| 文件页数： | 6/12页 |
| 文件大小： | 0K |
| 描述： | IC REG SWITCHED CAP DBL ADJ 6DFN |
| 标准包装： | 500 |
| 类型： | 切换式电容器（充电泵），倍增器 |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调 |
| 输入电压： | 1.8 V ~ 5.5 V |
| PWM 型： | Burst Mode? |
| 频率 - 开关： | 600kHz |
| 电流 - 输出： | 60mA |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-WFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 6-DFN-EP（2x2） |
LTC3221/
LTC3221-3.3/LTC3221-5
PI FU CTIO S
C+ (Pin 1): Flying Capacitor Positive Terminal.
C– (Pin 2): Flying Capacitor Negative Terminal.
? ? ?
? S H D N (Pin 3) (LTC3221-3.3/LTC3221-5) : Active Low
Shutdown Input. A low on S ? H ? D ? N ? disables the LTC3221-3.3/
LTC3221-5. S ? H ? D ? N ? must not be allowed to ?oat.
FB (Pin 3) (LTC3221): Feedback. The voltage on this pin
is compared to the internal reference voltage (1.23V) by
the error comparator to keep the output in regulation. An
external resistor divider is required between V OUT and FB
to program the output voltage.
BLOCK DIAGRA
LTC3221-3.3/LTC3221-5
GND (Pin 4): Ground. Should be tied to a ground plane
for best performance.
V IN (Pin 5): Input Supply Voltage. V IN should be bypassed
with a 2.2μF low ESR capacitor.
V OUT (Pin 6): Regulated Output Voltage. For best perfor-
mance, V OUT should be bypassed with a 2.2μF or higher
low ESR capacitor as close as possible to the pin.
Exposed Pad (Pin 7) Ground. The exposed pad must be
soldered to PCB ground to provide electrical contact and
optimum thermal performance.
LTC3221
V OUT
6
V OUT
6
2
1
C +
2
1
C +
+
CMP
1
I SW
5
V IN
FB
3
+
CMP
1
I SW
5
V IN
–
CONTROL
2
2
C –
–
CONTROL
2
2
C –
V REF
1
1
4
GND
V REF
4
GND
SHDN
3
3221 BD
OPERATIO
(Refer to Block Diagrams)
The LTC3221 family uses a switched capacitor charge pump
to boost V IN to a regulated output voltage. Regulation is
achieved by monitoring the output voltage, V OUT using a
comparator (CMP in the Block Diagram) and keeping it
within a hysteresis window. If V OUT drops below the lower
trip point of CMP, V OUT is charged by the controlled cur-
rent, I SW in series with the ?ying capacitor C FLY . Once V OUT
goes above the upper trip point of CMP, or if the upper
trip point is not reached after 0.8μs, C FLY is disconnected
from V OUT . The bottom plate of C FLY is then connected
to GND to allow I SW to replenish the charge on C FLY for
0.8μs. After which, I SW is turned off to keep the operating
supply current low. CMP continues to monitor V OUT and
turns on I SW if the lower threshold is reached again.
6
Shutdown Mode
The ? S ? H ? D ? N pin is a CMOS input with a threshold voltage
of approximately 0.8V. The LTC3221-3.3/ LTC3221-5 are
in shutdown when a logic low is applied to the ? S ? H ? D ? N
pin. In shutdown mode, all circuitry is turned off and the
LTC3221-3.3/ LTC3221-5 draw only leakage current from
the V IN supply. Furthermore, V OUT is disconnected from
V IN . Since the ? S ? H ? D ? N pin is a very high impedance CMOS
input, it should never be allowed to ?oat.
When ? S ? H ? D ? N is asserted low, the charge pump is ?rst dis-
abled, but the LTC3221-3.3/LTC3221-5 continue to draw
5μA of supply current. This current will drop to zero when
the output voltage (V OUT ) is fully discharged to 0V.
3221f
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