参数资料
型号: LTC3251EMSE-1.5#TRPBF
厂商: Linear Technology
文件页数: 10/16页
文件大小: 0K
描述: IC REG BUCK SWITCHED CAP 10MSOP
标准包装: 2,500
类型: 降压(降压),切换电容(充电泵)
输出类型: 固定
输出数: 1
输出电压: 1.5V
输入电压: 2.7 V ~ 5.5 V
PWM 型: 多重
频率 - 开关: 1MHz ~ 1.6MHz
电流 - 输出: 500mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 10-MSOP
LTC3251/
LTC3251-1.2/LTC3251-1.5
OPERATIO
(Refer to Block Diagram)
capacitor selection, etc.), the part’s burst current is set by
the burst threshold and hysteresis. This means that the
V OUT ripple voltage in Burst Mode operation will be fixed
and is typically 15mV with a 10 μ F output capacitor.
Ultralow Current Super Burst Mode Operation
To further optimize the supply current for low output
current requirements, a Super Burst mode operaton is
included in the LTC3251 family of parts. This mode is very
similar to Burst Mode operation, but much of the internal
circuitry and switch is shut down to further reduce supply
current. In Super Burst mode operation an internal hyster-
etic comparator is used to enable/disable charge transfer.
The hysteresis of the comparator and the amount of
current deliverable to the output are limited to keep output
Diagram, the LTC3251 family uses a control loop to adjust
the strength of the charge pump to match the current
required at the output. The error signal of this loop is
stored directly on the output charge storage capacitor.
Thus the charge storage capacitor also serves to form the
dominant pole for the control loop. The desired output
voltage also affects stability. As the divider ratio (R A /R B )
drops, the effective closed-loop gain increases, thus re-
quiring a larger output capacitor for stability. Figure 3
shows the suggested output capacitor for optimal tran-
sient response. The value of the output capacitance should
not drop below the minimum capacitance line to prevent
excessive ringing or instability. (see Ceramic Capacitor
Selection Guidelines section).
ripple low. The V OUT ripple voltage in Super Burst mode
operation is typically 35mV with a 10 μ F output capacitor.
The LTC3251 family can deliver 40mA of current in Super
Burst mode operation but does not switch to continuous
mode. The MODE pin of the LTC3251-1.2 and LTC3251-
1.5 has no effect on operation in super-burst mode.
V OUT Capacitor Selection
The style and value of capacitors used with the LTC3251
16
15
14
13
12
11
10
9
8
7
6
5
OPTIMUM CAPACITANCE
MINIMUM CAPACITANCE
family determine several important parameters such as
regulator control loop stability, output ripple and charge
pump strength.
4
0.9
1.0
1.1
1.2 1.3
V OUT (V)
1.4
1.5 1.6
3251 F03
The dual phase nature of the LTC3251 family minimizes
output noise significantly but not completely. What small
ripple that does exist is controlled by the value of C OUT
directly. Increasing the size of C OUT will proportionately
reduce the output ripple. The ESR (equivalent series
Figure 3
Likewise excessive ESR on the output capacitor will tend
to degrade the loop stability. The closed loop output
impedance of the LTC3251 is approximately:
resistance) of C OUT plays the dominant role in output
noise. When a part switches between clock phases there
is a period where all switches are turned off. This “blanking
R O ? 0 . 045 ? ?
V OUT
0 . 8 V
period” shows up as a spike at the output and is a direct
function of the output current times the ESR value. To
reduce output noise and ripple, it is suggested that a low
ESR (<0.08 ? ) ceramic capacitor be used for C OUT . Tanta-
lum and aluminum capacitors are not recommended be-
cause of their high ESR.
Both the style and value of C OUT can significantly affect the
stability of the LTC3251 family. As shown in the Block
For example, with the output programmed to 1.5V, the R O
is 0.085 ? , which produces a 40mV output change for a
500mA load current step. For stability and good load
transient response, it is important for the output capacitor
to have 0.08 ? or less of ESR. Ceramic capacitors typically
have exceptional ESR, and combined with a tight board
layout, should yield excellent stability and load transient
performance.
32511215fb
10
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