参数资料
型号: LTC3406BES5-1.2#TRMPBF
厂商: Linear Technology
文件页数: 10/12页
文件大小: 0K
描述: IC REG BUCK SYNC 1.2V TSOT23-5
标准包装: 500
类型: 降压(降压)
输出类型: 固定
输出数: 1
输出电压: 1.2V
输入电压: 2.5 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 1.5MHz
电流 - 输出: 600mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SOT-23-5 细型,TSOT-23-5
包装: 带卷 (TR)
供应商设备封装: TSOT-23-5
其它名称: LTC3406BES5-1.2#PBF
LTC3406BES5-1.2#PBF-ND
LTC3406B-1.2
APPLICATIO S I FOR ATIO
The regulator loop then acts to return V OUT to its steady-
state value. During this recovery time V OUT can be moni-
tored for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1 μ F) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C OUT , causing a rapid drop in V OUT . No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
3. Keep the (–) plates of C IN and C OUT as close as possible.
Design Example
As a design example, assume the LTC3406B-1.2 is used
in a single lithium-ion battery-powered cellular phone
application. The V IN will be operating from a maximum of
4.2V down to about 2.7V. The load current requirement
is a maximum of 0.6A but most of the time it will be in
standby mode, requiring only 2mA. Efficiency at both low
and high load currents is important. With this informa-
tion we can calculate L using equation (1),
1 . 2 V ? 1 ?
V IN ?
solutionistolimittherisetimeoftheswitchdrivesothat
the load rise time is limited to approximately (25 ? C LOAD ).
Thus, a 10 μ F capacitor charging to 3.3V would require a
L =
1
( f ) ( ? I L )
?
?
1 . 2 V ?
?
(3)
250 μ s rise time, limiting the charging current to about
130mA.
Substituting V IN = 4.2V, ? I L = 240mA and f = 1.5MHz in
equation (3) gives:
? 1 ?
? = 2 . 38 μ H
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
L =
1 . 2 V ?
1 . 5 MHz ( 240 mA ) ?
1 . 2 V ?
4 . 2 V ?
LTC3406B-1.2. These items are also illustrated graphi-
cally in Figures 3 and 4. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace and the V IN trace should be kept short, direct and
wide.
2. Does the (+) plate of C IN connect to V IN as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
A 2.2 μ H inductor works well for this application. For best
efficiency choose a 720mA or greater inductor with less
than 0.2 ? series resistance.
C IN will require an RMS current rating of at least 0.3A ?
I LOAD(MAX) /2 at temperature and C OUT will require an ESR
of less than 0.25 ? . In most cases, a ceramic capacitor will
satisfy this requirement.
1
RUN
VIA TO V OUT
VIA TO V IN
V IN
LTC3406B-1.2
2
GND V OUT
5
PIN 1
V OUT
+
C OUT
L1
3
SW
V IN
C IN
4
V OUT
L1
SW
LTC3406B-1.2
V IN
3406B12 F03
BOLD LINES INDICATE HIGH CURRENT PATHS
C OUT
GND
C IN
3406B12 F04
Figure 3. LTC3406B-1.2 Layout Diagram
Figure 4. LTC3406B-1.2 Suggested Layout
sn3406b12 3406b12fs
10
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