参数资料
型号: LTC3416EFE#TRPBF
厂商: Linear Technology
文件页数: 12/16页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 4A 20TSSOP
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 5 V
输入电压: 2.25 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 1MHz
电流 - 输出: 4A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 20-TSSOP-EP
LTC3416
APPLICATIO S I FOR ATIO
The R DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain I 2 R losses, simply add R SW
to R L and multiply the result by the square of the
average output current.
Other losses including C IN and C OUT ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
In most applications, the LTC3416 does not dissipate
much heat due to its high efficiency. But in applications
where the LTC3416 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such as
in dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction tempera-
ture reaches approximately 150 ° C, both power switches
will be turned off and the SW node will become high
impedance.
To avoid the LTC3416 from exceeding the maximum
When a load step occurs, V OUT immediately shifts by an
amount equal to ? I LOAD (ESR), where ESR is the effective
series resistance of C OUT . ? I LOAD also begins to charge or
discharge C OUT generating a feedback error signal used by
the regulator to return V OUT to its steady-state value.
During this recovery time, V OUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The I TH pin external components and output capaci-
tor shown in figure 1a will provide adequate compensation
for most applications.
Design Example
As a design example, consider using the LTC3416 in an
application with the following specifications: V IN = 3.3V,
V OUT1 = 1.8V, V OUT2 = 2.5V, I OUT1(MAX) = I OUT2(MAX) = 4A,
f = 1MHz. V OUT1 and V OUT2 must track when powering up
and powering down.
First, calculate the timing resistor:
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
R OSC =
3 . 08 ? 10 11
1 ? 10 6
– 10 k = 298 k
maximumjunctiontemperatureofthepart.Thetempera-
ture rise is given by:
Use a standard value of 294k ? . Next, calculate the induc-
tor values for about 40% ripple current:
L 1 = ?
? ? 1 –
L 2 = ?
? ? 1 –
? = 0 . 51 μ H
? = 0 . 38 μ H
T R = (P D )(θ JA )
where P D is the power dissipated by the regulator and θ JA
is the thermal resistance from the junction of the die to the
ambient temperature. For the 20-lead exposed TSSOP
package, the θ JA is 38 ° C/W.
? 1 . 8 V ? ?
? 1 MHz ? 1 . 6 A ? ?
? 2 . 5 V ? ?
? 1 MHz ? 1 . 6 A ? ?
1 . 8 V ?
3 . 3 V ?
2 . 5 V ?
3 . 3 V ?
The junction temperature, T J , is given by:
T J = T A + T R
Using a 0.47 μ H inductor for both results in maximum
ripple currents of:
? I L 1 = ?
? = 1 . 74 A
? I L 2 = ?
? = 1 . 29 A
where T A is the ambient temperature.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R DS(ON) ).
To maximize the thermal performance of the LTC3416, the
Exposed Pad should be soldered to a ground plane.
? 1 . 8 V ? ?
? 2 . 5 V ? ?
? ?
? ?
? 1 MHz ? 0 . 47 μ H ? ? 1 –
? 1 MHz ? 0 . 47 μ H ? ? 1 –
1 . 8 V ?
3 . 3 V ?
2 . 5 V ?
3 . 3 V ?
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current.
C OUT1 and C OUT2 will be selected based on the ESR that is
required to satisfy the output voltage ripple requirement
and the bulk capacitance needed for loop stability. For this
design, two 100 μ F ceramic capacitors will be used at each
output.
3416fa
12
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