参数资料
| 型号： | LTC3426ES6#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 5/12页 |
| 文件大小： | 0K |
| 描述： | IC REG BOOST ADJ 2A TSOT23-6 |
| 标准包装： | 2,500 |
| 类型： | 升压（升压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 2.25 V ~ 5.5 V |
| 输入电压： | 1.6 V ~ 4.3 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1.2MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-6 细型，TSOT-23-6 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | TSOT-23-6 |
LTC3426
OPERATIO
The LTC3426 is a monolithic 1.2MHz boost converter
housed in a 6-lead SOT-23 package. The device features
fixed frequency, current mode PWM control for excellent
line and load regulation. The low R DS(ON) NMOS switch
enables the device to maintain high efficiency over a wide
range of load current. Operation of the feedback loop
which sets the peak inductor current to keep the output in
regulation can be best understood by referring to the Block
Diagram in Figure 1. At the start of each clock cycle a latch
in the PWM logic is set and the NMOS switch is turned on.
The sum of a voltage proportional to the switch current
and a slope compensating voltage ramp is fed to the
positive input to the PWM comparator. When this voltage
exceeds either a voltage proportional to the 2A current
limit or the PWM control voltage, the latch in the PWM
logic is reset and NMOS switch is turned off. The PWM
APPLICATIO S I FOR ATIO
Setting the Output Voltage
The output voltage, V OUT , is set by a resistive divider from
V OUT to ground. The divider tap is tied to the FB pin. V OUT
is set by the formula:
control voltage at the output of the error amplifier is the
amplified and compensated difference between the feed-
back voltage on the FB pin and the internal reference
voltage of 1.22V. If the control voltage increases, more
current is delivered to the output. When the control voltage
exceeds the I LIMIT reference voltage, the peak current is
limited to a minimum of 2A. The current limit helps protect
the LTC3426 internal switch and external components
connected to it. If the control voltage decreases, less
current is delivered to the output. During load transients
control voltage may decrease to the point where no
switching occurs until the feedback voltage drops below
the reference. The LTC3426 has an integrated soft-start
feature which slowly ramps up the feedback control node
from 0V. The soft-start is initiated when SHDN is pulled
high.
to reduce the I 2 R power losses, and must be able to
handle the peak inductor current without saturating.
Several inductor manufacturers are listed in Table 1.
Table 1. Inductor Manufacturers
V OUT = 1 . 22 ? ? 1 +
?
?
?
R 1 ?
R 2 ?
TDK
Sumida
Murata
www.tdk.com
www.sumida.com
www.murata.com
Inductor Selection
The LTC3426 can utilize small surface mount inductors
due to its 1.2MHz switching frequency. A 1.5 μ H or 2.2 μ H
inductor will be the best choice for most LTC3426 appli-
cations. Larger values of inductance will allow greater
output current capability by reducing the inductor ripple
current. Increasing the inductance above 3.3 μ H will in-
crease component size while providing little improve-
ment in output current capability. The inductor current
ripple is typically set for 20% to 40% of the maximum
inductor current (I P ). High frequency ferrite core inductor
materials reduce frequency dependent power losses com-
pared to cheaper powdered iron types, improving effi-
ciency. The inductor should have low DCR (DC resistance)
Output and Input Capacitor Selection
Low ESR (equivalent series resistance) capacitors should
be used to minimize the output voltage ripple. Multilayer
ceramic capacitors are an excellent choice as they have
extremely low ESR and are available in small footprints. A
15 μ F to 30 μ F output capacitor is sufficient for most
applications. X5R and X7R dielectric materials are pre-
ferred for their ability to maintain capacitance over wide
voltage and temperature ranges.
Low ESR input capacitors reduce input switching noise
and reduce the peak current drawn from the input supply.
It follows that ceramic capacitors are also a good choice
for input decoupling and should be located as close as
3426fa
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