参数资料
型号: LTC3441EDE#PBF
厂商: Linear Technology
文件页数: 5/16页
文件大小: 0K
描述: IC REG BUCK BOOST SYNC ADJ 12DFN
标准包装: 91
类型: 降压(降压),升压(升压)
输出类型: 可调式
输出数: 1
输出电压: 2.4 V ~ 5.25 V
输入电压: 2.4 V ~ 5.5 V
PWM 型: Burst Mode?
频率 - 开关: 1MHz
电流 - 输出: 1.2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 12-WFDFN 裸露焊盘
包装: 管件
供应商设备封装: 12-DFN(4x3)
产品目录页面: 1334 (CN2011-ZH PDF)
LTC3441
TYPICAL PERFOR A CE CHARACTERISTICS
NMOS R DS(ON)
PMOS R DS(ON)
Minimum Start Voltage
0.15
0.13
V IN = V OUT = 3.6V
SWITCHES B AND C
0.15
0.14
0.13
V IN = V OUT = 3.6V
SWITCHES A AND D
2.30
2.25
0.12
0.11
0.11
0.10
2.20
0.09
0.09
0.08
2.15
0.07
0.07
0.06
0.05
–55
–25
5 35 65
TEMPERATURE ( ° C)
95
125
0.05
–50
–25
5 35 65
TEMPERATURE ( ° C)
95
125
2.10
–55
–25
5 35 65
TEMPERATURE ( ° C)
95
125
PI FU CTIO S
3441 G14
3441 G15
3441 G16
SHDN/SS (Pin 1): Combined Soft-Start and Shutdown.
Applied voltage < 0.4V shuts down the IC. Tie to >1.4V to
enable the IC and >2.4V to ensure the error amp is not
clamped from soft-start. An RC from the shutdown com-
mand signal to this pin will provide a soft-start function by
limiting the rise time of the V C pin.
GND (Pin 2): Signal Ground for the IC.
PGND (Pins 3, 6, 13 Exposed Pad): Power Ground for the
Internal NMOS Power Switches
SW1 (Pin 4): Switch pin where the internal switches A and
B are connected. Connect inductor from SW1 to SW2. An
optional Schottky diode can be connected from this SW1
to ground. Minimize trace length to keep EMI down.
SW2 (Pin 5): Switch pin where the internal switches C
and D are connected. An optional Schottky diode can be
connected from SW2 to V OUT (it is required where
V OUT > 4.3V). Minimize trace length to keep EMI down.
MODE/SYNC (Pin 7): Burst Mode Select and Oscillator
Synchronization.
MODE/SYNC = High: Enable Burst Mode Operation.
During the period where the IC is supplying energy to
the output, the inductor peak inductor current will reach
0.8A and return to zero current on each cycle. In Burst
Mode operation the operation is variable frequency,
which provides a significant efficiency improvement at
light loads. The Burst Mode operation will continue until
the pin is driven low.
MODE/SYNC = Low: Disable Burst Mode operation and
maintain low noise, constant frequency operation .
MODE/SYNC = External CLK : Synchronization of the
internal oscillator and Burst Mode operation disable. A
clock pulse width between 100ns and 2 μ s and a clock
frequency between 2.3MHz and 3.4MHz (twice the
desired frequency) is required to synchronize the IC.
f OSC = f SYNC /2
V OUT (Pin 8): Output of the Synchronous Rectifier. A filter
capacitor is placed from V OUT to GND. A ceramic bypass
capacitor is recommended as close to the V OUT and GND
pins as possible.
PV IN (Pin 9): Power V IN Supply Pin. A 10 μ F ceramic capaci-
tor is recommended as close to the PV IN and PGND pins
as possible
V IN (Pin 10): Input Supply Pin. Internal V CC for the IC.
V C (Pin 11): Error Amp Output. A frequency compensation
network is connected from this pin to the FB pin to
compensate the loop. See the section “Compensating the
Feedback Loop” for guidelines.
FB (Pin 12): Feedback Pin. Connect resistor divider tap
here. The output voltage can be adjusted from 2.4V to
5.25V. The feedback reference voltage is typically 1.22V.
3441fa
5
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