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参数资料
| 型号： | LTC3448EMS8E#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 0.6A 8MSOP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 5.2 V |
| 输入电压： | 2.5 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1.5MHz ~ 2.25MHz |
| 电流 - 输出： | 600mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 8-MSOP-EP |
LTC3448
APPLICATIO S I FOR ATIO
top and bottom MOSFET R DS(ON) and the duty cycle
(DC) as follows:
R SW = (R DS(ON)TOP )(DC) + (R DS(ON)BOT )(1 – DC)
The R DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain I 2 R losses, simply add R SW
to R L and multiply the result by the square of the
average output current.
3. At load currents below the selected threshold the
LTC3448 will switch into low ripple LDO mode if en-
abled. In this case the losses are due to the DC bias
currents as given in the electrical characteristics and
I 2 R losses due to the (V IN – V OUT ) voltage drop across
the internal pass transistor.
Other losses when in switching operation, including C IN
and COUT ESR dissipative losses and inductor core losses,
generally account for less than 2% total additional loss.
Thermal Considerations
The LTC3448 requires the package backplane metal (GND
pin) to be well soldered to the PC board. This gives the DFN
and MSOP packages exceptional thermal properties, mak-
ing it difficult in normal operation to exceed the maximum
junction temperature of the part. In most applications the
LTC3448 does not dissipate much heat due to its high
efficiency. In applications where the LTC3448 is running at
high ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part if it
is not well thermally grounded. If the junction temperature
reaches approximately 150 ° C, both power switches will be
turned off and the SW node will become high impedance.
To avoid the LTC3448 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T R = P D θ JA
where P D is the power dissipated by the regulator and θ JA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, T J , is given by:
T J = T A + T R
where T A is the ambient temperature.
As an example, consider the LTC3448 in dropout at an
input voltage of 2.7V, a load current of 600mA and an
ambient temperature of 70 ° C. From the typical perfor-
mance graph of switch resistance, the R DS(ON) of the
P-channel switch at 70 ° C is approximately 0.52 ? . There-
fore, power dissipated by the part is:
P D = I LOAD2 ? R DS(ON) = 187.2mW
For the 3mm × 3mm DFN package, the θ JA is 43 ° C/W.
Thus, the junction temperature of the regulator is:
T J = 85 ° C + (0.1872)(43) = 93 ° C
which is well below the maximum junction temperature of
125 ° C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance R DS(ON).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V OUT immediately shifts by an amount
equal to ( ? I LOAD ? ESR), where ESR is the effective series
resistance of C OUT . ? I LOAD also begins to charge or dis-
charge C OUT , which generates a feedback error signal. The
regulator loop then acts to return V OUT to its steady-state
value. During this recovery time V OUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. For a detailed explanation of switching control loop
theory, see Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1 μ F) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
3448f
12
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