参数资料
型号: LTC3546IFE#TRPBF
厂商: Linear Technology
文件页数: 16/30页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ DL 28TSSOP
标准包装: 2,000
类型: 降压(降压)
输出类型: 可调式
输出数: 2
输出电压: 0.6 V ~ 5 V
输入电压: 2.25 V ~ 5.5 V
PWM 型: 电流模式,混合
频率 - 开关: 2.25MHz,750kHz ~ 4MHz
电流 - 输出: 1A,2A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 28-TSSOP 裸露焊盘
LTC3546
APPLICATIONS INFORMATION
the maximum RMS current. The RMS current calculation
is different if the part is used in-phase or out-of-phase.
For in-phase, there are two different equations:
V OUT1 > V OUT2 :
when V OUT1 – V IN /2 = V OUT2 and when V OUT2 – V IN /2 =
V OUT1 . As a good rule of thumb, the amount of worst-case
ripple is about 75% of the worst-case ripple in the in-phase
mode. Note, that when V OUT1 = V OUT2 = V IN /2 and I 1 = I 2 ,
the ripple is at its minimum.
I RMS =
V OUT2 > V OUT1 :
I RMS =
2 ? I1 ? I2 ? D2 ( 1–D1 ) + I2 2 ( D2 –D2 2 ) + I1 2 ( D1–D1 2
2 ? I1 ? I2 ? D1 ( 1–D2 ) + I2 2 ( D2 –D2 2 ) + I1 2 ( D1–D1 2
)
)
Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours lifetime. This makes
it advisable to further derate the capacitor, or choose a
capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet the
size or height requirements of the design. An additional
0.1μF to 1μF ceramic capacitor is also recommended on
V IN for high frequency decoupling, when not using an all
ceramic capacitor solution.
D1 = OUT1 and D2 = OUT2
V OUT ( V IN – V OUT )
I RMS = ( I1 + I2 )
I1 = I LIM1 –
Δ V OUT ≈ Δ I L ? ESR +
Δ I L2
I2 = I LIM2 –
Where:
V V
V IN V IN
When D1 = D2, then the equation simplifies to:
I RMS = ( I1 + I2 ) D ( 1–D )
or
V IN
where the maximum average output currents I1 and
I2 equals the peak current minus half the peak-to-peak
ripple current:
Δ I L1
2
2
These formula have a maximum at V IN = 2V OUT , where
I RMS = (I1 + I2)/2. This simple worst-case is commonly
used to determine the worst-case I RMS .
For out-of-phase (PHASE pin is at ground), the ripple
current can be lower than the in-phase.
In the out-of-phase case, the maximum I RMS does not oc-
cur when V OUT1 = V OUT2 . The maximum typically occurs
Output Capacitor (C OUT1 and C OUT2 ) Selection
The selection of C OUT1 and C OUT2 is driven by the required
ESR to minimize voltage ripple and load step transients.
Typically, once the ESR requirement is satisfied, the
capacitance is adequate for filtering. The output ripple
( Δ V OUT ) is determined by:
? 1 ?
?
? 8 ? f O ? C OUT ?
where f O = operating frequency, C OUT = output capacitance
and Δ I L = ripple current in the inductor. The output ripple
is highest at maximum input voltage since Δ I L increases
with input voltage.
Once the ESR requirements for C OUT have been met, the
RMS current rating generally far exceeds the I RIPPLE(P-P)
requirement, except for an all ceramic solution.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Aluminum
electrolytic, special polymer, ceramic and dry tantalum
capacitors are all available in surface mount packages.
The OS-CON semiconductor dielectric capacitor avail-
able from Sanyo has the lowest ESR(size) product of any
aluminum electrolytic at a somewhat higher price. Special
polymer capacitors, such as Sanyo POSCAP, offer very
low ESR, but have a lower capacitance density than other
types. Tantalum capacitors have the highest capacitance
16
For more information www.linear.com/3546
3546fc
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