参数资料
型号: LTC3549EDCB#TRPBF
厂商: Linear Technology
文件页数: 13/16页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 0.25A 6DFN
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.61 V ~ 5.5 V
输入电压: 1.6 V ~ 5.5 V
PWM 型: 电流模式,混合
频率 - 开关: 2.25MHz
电流 - 输出: 250mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 6-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 6-DFN-EP(2x3)
LTC3549
APPLICATIO S I FOR ATIO
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3549. These items are also illustrated graphically
in the layout diagram of Figure 3. Check the following in
your layout.
1. Does the capacitor C IN connect to the power V IN (Pin 1)
and GND (Pins 2, 7) as close as possible? This capacitor
provides the AC current to the internal power MOSFETs
and their drivers.
2. Are the C OUT and L1 closely connected? The (–) plate of
C OUT returns current to GND and the (–) plate of C IN .
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C OUT and a ground sense line
terminated near GND (Exposed Pad). The feedback
Figure 3a. Buck Regulator Top Layer
signals V FB should be routed away from noisy compo-
nents and traces, such as the SW line (Pin 3), and its
trace should be minimized.
4. Keep sensitive components away from the SW pins.
The input capacitor C IN and the resistors R1 and R2
should be routed away from the SW traces and the
inductors.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GND pin at one
point. They should not share the high current path of
C IN or C OUT .
6. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to V IN or G ND .
Figure 3b. Buck Regulator Bottom Layer
3549f
13
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