参数资料
型号: LTC3550EDHC-1#PBF
厂商: Linear Technology
文件页数: 17/24页
文件大小: 0K
描述: IC CHARGER BATT DUAL 16-DFN
标准包装: 73
功能: 充电管理
电池化学: 锂离子(Li-Ion)
电源电压: 4.3 V ~ 8 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-WFDFN 裸露焊盘
供应商设备封装: 16-DFN(5x3)
包装: 管件
LTC3550-1
APPLICATIO S I FOR ATIO
Using Ceramic Input and Output Capacitors
Higher capacitance values, lower cost ceramic capacitors
are now becoming available in smaller case sizes. Their
high ripple current, high voltage rating and low ESR make
them ideal for switching regulator applications. Because the
LTC3550-1’s control loop does not depend on the output
capacitor’s ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
Ef?ciency Considerations
The ef?ciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the ef?ciency and which change would produce
the most improvement. Ef?ciency can be expressed as:
Ef?ciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses in LTC3550-1 circuits: V CC quiescent current
and I 2 R losses. The V CC quiescent current loss dominates
the ef?ciency loss at very low load currents whereas the
I 2 R loss dominates the ef?ciency loss at medium to high
load currents. In a typical ef?ciency plot, the ef?ciency
than the DC bias current. In continuous mode, I GATECHG
= f(Q T + Q B ) where Q T and Q B are the gate charges of
the internal top and bottom switches. Both the DC bias
and gate charge losses are proportional to V CC and
thus their effects will be more pronounced at higher
supply voltages.
2. I 2 R losses are calculated from the resistances of the
internal switches, R SW , and external inductor R L . In
continuous mode, the average output current ?owing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R DS(ON) and the duty cycle
(DC) as follows:
R SW = (R DS(ON)TOP )(DC) + (R DS(ON)BOT )(1 – DC)
The R DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I 2 R losses, simply add R SW to R L
and multiply the result by the square of the average output
current. Other losses including C IN and C OUT ESR dissipa-
tive losses and inductor core losses generally account for
less than 2% total additional loss.
1
0.1
0.01
0.001
0.0001
curve at very low load currents can be misleading since
the actual power lost is of no consequence as illustrated
in Figure 3.
0.00001
0.1
1
10 100
LOAD CURRENT (mA)
1000
3550-1 F03
1. The V CC quiescent current is due to two components:
Figure 3. Power Lost vs Load Current
the DC bias current as given in the Electrical Charac-
teristics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate
is switched from high to low to high again, a packet of
charge, dQ, moves from V CC to ground. The resulting
dQ/dt is the current out of V CC that is typically larger
35501f
17
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