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参数资料
| 型号： | LTC3554EPD#TRPB |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | 0.5 A BATTERY CHARGE CONTROLLER, 1295 kHz SWITCHING FREQ-MAX, PQCC20 |
| 封装： | 3 X 3 MM, 0.55 MM HEIGHT, LEAD FREE, PLASTIC, UTQFN-20 |
| 文件页数： | 19/36页 |
| 文件大小： | 418K |
| 代理商： | LTC3554EPD#TRPB |
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LTC3554
26
3554p
In the HR state, all supplies are disabled. The PowerPath
circuitry is placed in an ultralow quiescent state to minimize
battery drain. If no external charging supply is present
(VBUS) then the ideal diode is shut down, disconnecting
VOUT from BAT to further minimize battery drain. The ultra-
low power consumption in the HR state makes it ideal for
shipping or long term storage, minimizing battery drain.
The following events cause the state machine to transition
out of HR into the power-up (PUP1) state:
ON input low for 400ms (PB400MS)
Application of external power (EXTPWR)
Upon entering the PUP1 state, the pushbutton circuitry
will sequence up the two step-down switching regulators,
buck1 followed by buck2. The PWR_ON1 and PWR_ON2
inputs are ignored in the PUP1 state. The state machine
remains in the PUP1 state for ve seconds. During the
ve seconds, the application’s microprocessor, powered
by the switching regulators, has time to boot and assert
PWR_ON1 and/or PWR_ON2. Five seconds after entering
the PUP1 state, the pushbutton circuitry automatically
transitions into the power-on (PON) state.
In the PON state, the switching regulators can be en-
abled and shut down at any time by the PWR_ON1 and
PWR_ON2 pins. A high on PWR_ON1 is needed to keep
buck1 enabled, and a high on PWR_ON2 is needed to
keep buck2 enabled. To remain in the PON state, the ap-
plication circuit must keep at least one of the PWR_ON
inputs high, else the state machine enters the power-down
(PDN2) state.
When PWR_ON1 and PWR_ON2 are both low, or when
VOUT drops to its undervoltage lockout (VOUT UVLO)
threshold, the state machine will leave the PON state and
enter the power-down (PDN2) state. In the power-down
OPERATION
state (PDN2), both switching regulators are kept disabled
regardless of the states of the PWR_ON pins. The state
machine remains in the power-down state for one second,
before automatically entering either the power-off (POFF)
state. This one second delay allows all LTC3554 generated
supplies time to power down completely before they can
be re-enabled.
The same events used to exit the hard reset (HR) state
are also used to exit the POFF state and enter the PUP2
state. The PUP2 state operates in the same manner as
the PUP1 state previously described.
Both bucks remain powered up during the ve second
power-up (PUP1 or PUP2) period, regardless of the state
of the PWR_ON inputs.
In either the HR or POFF states, if any PWR_ON pin is
driven high, the pushbutton circuitry directly enters the
PON state, without passing through the power-up (PUP1
or PUP2) states. This is because by asserting logic high
on the PWR_ON1 or PWR_ON2 pins, the application has
already told the LTC3554 exactly which buck(s) to turn
on, so there is no need for an intermediate PUP state in
which both bucks are enabled for ve seconds.
Starting from the HR state, bringing any PWR_ON pin
high enables the PowerPath, if it wasn’t already enabled
due to VBUS power being available. This powers up the
VOUT pin from VBUS or BAT. When the VOUT voltage rises
above the VOUT UVLO threshold, the state machine transi-
tions from the HR state into the PON state, allowing the
selected buck(s) to turn on.
The hard reset (HRST) event is generated by pressing
and holding the pushbutton (ON input low) for 5 seconds.
For a valid HRST event to occur the button press must
start in the PUP1, PUP2 or PON state, but can end in any
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