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参数资料
| 型号： | LTC3561EDD#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 1A 8DFN |
| 标准包装： | 121 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 5 V |
| 输入电压： | 2.63 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 最高 4MHz |
| 电流 - 输出： | 1A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 8-DFN-EP（3x3） |
| 产品目录页面： | 1335 (CN2011-ZH PDF) |
LTC3561
APPLICATIO S I FOR ATIO
reduces surge currents from V IN by gradually increasing
the peak inductor current. Power supply sequencing can
also be accomplished using this pin. The LTC3561 has an
internal digital soft-start which steps up a clamp on I TH
over 1024 clock cycles, as can be seen in Figure 3.
The soft-start time can be increased by ramping the
voltage on I TH during start-up as shown in Figure 2(c). As
the voltage on I TH ramps through its operating range the
internal peak current limit is also ramped at a proportional
linear rate.
Checking Transient Response
The OPTI-LOOP compensation allows the transient re-
sponse to be optimized for a wide range of loads and
output capacitors. The availability of the I TH pin not only
allows optimization of the control loop behavior but also
provides a DC coupled and AC filtered closed loop re-
sponse test point. The DC step, rise time and settling at this
test point truly reflects the closed loop response. Assum-
ing a predominantly second order system, phase margin
and/or damping factor can be estimated using the percent-
age of overshoot seen at this pin. The bandwidth can also
be estimated by examining the rise time at the pin.
The I TH external components shown in the front page
circuit will provide an adequate starting point for most
applications. The series R-C filter sets the dominant pole-
zero loop compensation. The values can be modified
slightly (from 0.5 to 2 times their suggested values) to
optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
the loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise time
of 1 μ s to 10 μ s will produce output voltage and I TH pin
waveforms that will give a sense of the overall loop
stability without breaking the feedback loop.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V OUT
immediately shifts by an amount equal to ? I LOAD ? ESR,
where ESR is the effective series resistance of C OUT .
? I LOAD also begins to charge or discharge C OUT generat-
ing a feedback error signal used by the regulator to return
V OUT to its steady-state value. During this recovery time,
V OUT can be monitored for overshoot or ringing that would
indicate a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C. If
R is increased by the same factor that C is decreased, the
zero frequency will be kept the same, thereby keeping the
phase the same in the most critical frequency range of the
feedback loop. In addition, a feedforward capacitor C F can
be added to improve the high frequency response, as
shown in Figure 5. Capacitor C F provides phase lead by
creating a high frequency zero with R2 which improves the
phase margin.
SHDN/R T
R T
SHDN/R T
R T
SV IN
1M
V IN
RUN
3561 F03a
RUN
3561 F03b
2V/DIV
V OUT
(2a)
RUN OR V IN
R1 D1
I TH
R C
(2b)
2V/DIV
I L
500mA/DIV
V IN = 3.3V
C1
(2c)
C C
3561 F03c
200 μ s/DIV
V OUT = 2.5V
R L = 1.4 ?
3411 F04.eps
Figure 2. SHDN/R T Pin Interfacing and External Soft-Start
Figure 3. Digital Soft-Start
3561f
9
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