参数资料
型号: LTC3563EDC#TRMPBF
厂商: Linear Technology
文件页数: 11/16页
文件大小: 0K
描述: IC REG BUCK SYNC 0.5A 6DFN
标准包装: 500
类型: 降压(降压)
输出类型: 固定
输出数: 1
输出电压: 1.28V,1.87V
输入电压: 2.5 V ~ 5.5 V
PWM 型: 电流模式,混合
频率 - 开关: 2.25MHz
电流 - 输出: 500mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 6-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 6-DFN-EP(2x2)
LTC3563
APPLICATIO S I FOR ATIO
Ef?ciency Considerations
The ef?ciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the ef?ciency and which change would produce
the most improvement. Ef?ciency can be expressed as:
Ef?ciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of
the losses in LTC3563 circuits: 1) V IN quiescent current,
2) I 2 R loss and 3) switching loss. V IN quiescent current
loss dominates the power loss at very low load currents,
whereas the other two dominate at medium to high load
currents. In a typical ef?ciency plot, the ef?ciency curve
at very low load currents can be misleading since the
actual power loss is of no consequence as illustrated in
Figure 2.
1) The V IN quiescent current is the DC supply current given
in the Electrical Characteristics which excludes MOSFET
charging current. V IN current results in a small (<0.1%)
loss that increases with V IN , even at no load.
2) I 2 R losses are calculated from the DC resistances of
the internal switches, R SW , and external inductor, R L . In
continuous mode, the average output current ?ows through
inductor L, but is “chopped” between the internal top and
bottom switches. Thus, the series resistance looking into
the SW pin is a function of both top and bottom MOSFET
R DS(ON) and the duty cycle (D) as follows:
R SW = (R DS(ON)TOP )(D) + (R DS(ON)BOT )(1 – D)
The R DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I 2 R losses:
I 2 R losses = I OUT2 (R SW + R L )
3) The switching current is MOSFET gate charging current,
that results from switching the gate capacitance of the
power MOSFETs. Each time a MOSFET gate is switched
1000
100
10
1
V IN = 3.6V
from low to high to low again, a packet of charge dQ moves
from V IN to ground. The resulting dQ/dt is a current out of
V IN that is typically much larger than the DC bias current.
In continuous mode, I GATECHG = f O (Q T + Q B ), where Q T
and Q B are the gate charges of the internal top and bottom
MOSFET switches. The gate charge losses are proportional
to V IN and thus their effects will be more pronounced at
higher supply voltages.
0.1
0.1
V OUT = 1.87V
V OUT = 1.28V
1 10 100 1000
OUTPUT CURRENT (mA)
Other “hidden” losses such as copper trace and internal
battery resistances can account for additional ef?ciency
degradations in portable systems. The internal battery
3563 F02
Figure 2. Power Loss vs Load Current
and fuse resistance losses can be minimized by making
sure that C IN has adequate charge storage and very low
ESR at the switching frequency. Other losses include
diode conduction losses during dead-time and inductor
core losses generally account for less than 2% total ad-
ditional loss.
3563f
11
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