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| 型号： | LTC3563EDC |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | 1.75 A SWITCHING REGULATOR, 2700 kHz SWITCHING FREQ-MAX, PDSO6 |
| 封装： | 2 X 2 MM, PLASTIC, MO-229WCCD-2, DFN-6 |
| 文件页数： | 3/16页 |
| 文件大小： | 276K |
| 代理商： | LTC3563EDC |
LTC3563
11
3563f
Efciency Considerations
The efciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efciency and which change would produce
the most improvement. Efciency can be expressed as:
Efciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of
the losses in LTC3563 circuits: 1) VIN quiescent current,
2) I2R loss and 3) switching loss. VIN quiescent current
loss dominates the power loss at very low load currents,
whereas the other two dominate at medium to high load
currents. In a typical efciency plot, the efciency curve
at very low load currents can be misleading since the
actual power loss is of no consequence as illustrated in
Figure 2.
1) The VIN quiescent current is the DC supply current given
in the Electrical Characteristics which excludes MOSFET
charging current. VIN current results in a small (<0.1%)
loss that increases with VIN, even at no load.
2) I2R losses are calculated from the DC resistances of
the internal switches, RSW, and external inductor, RL. In
continuous mode, the average output current ows through
inductor L, but is “chopped” between the internal top and
bottom switches. Thus, the series resistance looking into
the SW pin is a function of both top and bottom MOSFET
RDS(ON) and the duty cycle (D) as follows:
RSW = (RDS(ON)TOP)(D) + (RDS(ON)BOT)(1 – D)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses:
I2R losses = IOUT
2(RSW + RL)
3) The switching current is MOSFET gate charging current,
that results from switching the gate capacitance of the
power MOSFETs. Each time a MOSFET gate is switched
from low to high to low again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is a current out of
VIN that is typically much larger than the DC bias current.
In continuous mode, IGATECHG = fO(QT + QB), where QT
and QB are the gate charges of the internal top and bottom
MOSFET switches. The gate charge losses are proportional
to VIN and thus their effects will be more pronounced at
higher supply voltages.
Other “hidden” losses such as copper trace and internal
battery resistances can account for additional efciency
degradations in portable systems. The internal battery
and fuse resistance losses can be minimized by making
sure that CIN has adequate charge storage and very low
ESR at the switching frequency. Other losses include
diode conduction losses during dead-time and inductor
core losses generally account for less than 2% total ad-
ditional loss.
APPLICATIO S I FOR ATIO
WU
UU
Figure 2. Power Loss vs Load Current
OUTPUT CURRENT (mA)
1
POWER
LOSS
(mW)
10
100
1000
0.1
10
100
1000
3563 F02
0.1
1
VOUT = 1.87V
VOUT = 1.28V
VIN = 3.6V
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