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参数资料
| 型号： | LTC3604IUD#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 7/24页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC 2.5A 16QFN |
| 标准包装： | 121 |
| 类型： | 降压（降压） |
| 输出数： | 1 |
| 输入电压： | 3.6 V ~ 15 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 800kHz ~ 4MHz |
| 电流 - 输出： | 2.5A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 16-QFN-EP（3x3） |
LTC3604
PIN FUNCTIONS
(QFN/MSE)
MODE/SYNC (Pin 1/Pin 15): Mode Selection and External
Synchronization Input Pin. This pin places the LTC3604
into forced continuous operation when tied to ground.
High ef?ciency Burst Mode operation is enabled by either
?oating this pin or by tying this pin to INTV CC . When driven
with an external clock, an internal phase-locked loop will
synchronize the phase and frequency of the internal oscil-
lator to that of the incoming clock signal. During external
clock synchronization, the LTC3604 will default to forced
continuous operation.
PGOOD (Pin 2/Pin 16): Open-Drain Power Good Output
Pin. PGOOD is pulled to ground when the voltage at the
FB pin is not within ±8% (typical) of the internal 0.6V
reference. PGOOD becomes high impedance once the
voltage at the FB pin returns to within ±5% (typical) of
the internal reference.
SW (Pins 3, 4/Pins 1, 2): Switch Node Output Pin. Con-
nect this pin to the SW side of the external inductor. The
normal operation voltage swing of this pin ranges from
ground to PV IN .
BOOST (Pin 6/Pin 5): Boosted Floating Driver Supply
Pin. The (+) terminal of the external bootstrap capacitor
connects to this pin while the (–) terminal connects to
the SW pin. The normal operation voltage swing of this
pin ranges from a diode voltage drop below INTV CC up
to PV IN + INTV CC .
INTV CC (Pin 7/Pin 6): Internal 3.3V Regulator Output Pin.
This pin should be decoupled to PGND with a low ESR
ceramic capacitor of 1μF or more.
V ON (Pin 8/Pin 7): On-Time Voltage Input Pin. This pin
sets the voltage trip point for the on-time comparator. Con-
nect this pin to the regulated output to make the on-time
proportional to the output voltage. The pin impedance is
normally 180kΩ.
SGND (Pin 9/Exposed Pad Pin 17): Signal Ground Pin.
This pin should have a low noise connection to reference
ground. The feedback resistor network, external compensa-
tion network and RT resistor should be connected to this
ground. In the MSE package, this pin must be soldered to
the PCB to provide a good thermal contact to the PCB.
RT (Pin 10/Pin 8): Oscillator Frequency Program Pin. Con-
nect an external resistor, between 80k to 400k, from this
pin to SGND to program the LTC3604 switching frequency
from 800kHz to 4MHz. When RT is tied to INTV CC , the
switching frequency will default to 2MHz.
FB (Pin 11/Pin 9): Output Voltage Feedback Pin. Input to
the error ampli?er that compares the feedback voltage to
the internal 0.6V reference voltage. Connect this pin to
the appropriate resistor divider network to program the
desired output voltage.
ITH (Pin 12/Pin 10): Error Ampli?er Output and Switching
Regulator Compensation Pin. Connect this pin to appro-
priate external components to compensate the regulator
loop frequency response. Connect this pin to INTV CC to
use the default internal compensation.
TRACK/SS (Pin 13/Pin 11): Output Voltage Tracking and
Soft-Start Input Pin. Forcing a voltage below 0.6V on
this pin overrides the internal reference input to the error
ampli?er. The LTC3604 will servo the FB pin to the TRACK
voltage under this condition. Above 0.6V, the tracking func-
tion stops and the internal reference resumes control of
the error ampli?er. An internal 1.4μA pull-up current from
INTV CC allows a soft-start function to be implemented by
connecting an external capacitor between this pin and
ground. See Applications Information section for more
details.
RUN (Pin 14/Pin 12): Regulator Enable Pin. Enables chip
operation by applying a voltage above 1.25V. A voltage
below 1V on this pin places the part into shutdown. Do
not ?oat this pin.
V IN (Pins 15, 16/Pins 13, 14): Main Power Supply Input
Pins. These pins should be closely decoupled to PGND
with a low ESR capacitor of 10μF or more.
PGND (Exposed Pad Pin 17/Pins 3, 4): Power Ground
Pin. The (–) terminal of the input bypass capacitor, C IN ,
and the (–) terminal of the output capacitor, C OUT , should
be tied to this pin with a low impedance connection. The
exposed package pad must be soldered to the PCB to
provide low impedance electrical contact to ground and
good thermal contact to the PCB.
3604f
7
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