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| 型号： | LTC3610IWP#TR |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING REGULATOR, PQCC64 |
| 封装： | 9 X 9 MM, PLASTIC, QFN-64 |
| 文件页数： | 8/24页 |
| 文件大小： | 388K |
| 代理商： | LTC3610IWP#TR |
LTC3610
3610ff
applications inForMation
4. CINloss.Theinputcapacitorhasthedifficultjoboffiltering
the large RMS input current to the regulator. It must have
a very low ESR to minimize the AC I2R loss and sufficient
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries.
Other losses, including COUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
CheckingTransientResponse
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to
ΔILOAD (ESR), where ESR is the effective series
resistance of COUT. ΔILOAD also begins to charge or dis-
chargeCOUTgeneratingafeedbackerrorsignalusedbythe
regulator to return VOUT to its steady-state value. During
this recovery time, VOUT can be monitored for overshoot
or ringing that would indicate a stability problem. The ITH
pin external components shown in Figure 6 will provide
adequate compensation for most applications. For a
detailed explanation of switching control loop theory see
Application Note 76.
DesignExample
As a design example, take a supply with the following
specifications: VIN = 5V to 24V (12V nominal), VOUT =
2.5V ±5%, IOUT(MAX) = 12A, f = 550kHz. First, calculate
the timing resistor with VON = VOUT:
R
kHz
pF
k
ON =
(
)(
)
=
1
550
10
182
and choose the inductor for about 40% ripple current at
the maximum VIN:
L =
2.5V
550kHz
(
) 0.4
(
) 12A
(
)
1
2.5V
28V
=
0.86H
Selectingastandardvalueof0.82Hresultsinamaximum
ripple current of:
ΔIL =
2.5V
550kHz
(
) 0.82H
(
)
1–
2.5V
12V
=
4.4A
Next, set up VRNG voltage and check the ILIMIT. Tying VRNG
to 0.5V will set the typical current limit to 16A, and tying
VRNG to GND will result in a typical current around 19A.
CIN is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR
of 0.013Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
ΔVOUT(RIPPLE) = ΔIL(MAX) (ESR)
= (4.4A) (0.013Ω) = 57mV
However, a 0A to 10A load step will cause an output
change of up to:
ΔVOUT(STEP) = ΔILOAD (ESR) = (10A) (0.013Ω) = 130mV
An optional 22F ceramic output capacitor is included
to minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 6.
How to Reduce SW Ringing
As with any switching regulator, there will be voltage ring-
ing on the SW node, especially for high input voltages.
The ringing amplitude and duration is dependent on the
switching speed (gate drive), layout (parasitic inductance)
and MOSFET output capacitance. This ringing contributes
to the overall EMI, noise and high frequency ripple. One
way to reduce ringing is to optimize layout. A good layout
minimizesparasiticinductance.AddingRCsnubbersfrom
SWtoGNDisalsoaneffectivewaytoreduceringing.Finally,
adding a resistor in series with the BOOST pin will slow
down the MOSFET turn-on slew rate to dampen ringing,
but at the cost of reduced efficiency. Note that since the
IC is buffered from the high frequency transients by PCB
and bondwire inductances, the ringing by itself is normally
not a concern for controller reliability.
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