参数资料
型号: LTC3615EFE-1#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 稳压器
英文描述: SWITCHING REGULATOR, PDSO24
封装: 4.40 MM, LEAD FREE, PLASTIC, TSSOP-24
文件页数: 8/32页
文件大小: 585K
代理商: LTC3615EFE-1#PBF
LTC3615/LTC3615-1
16
3615fa
LTC3615
SVIN
VIN
RT/SYNC
LTC3615
SVIN
VIN
0.4V
RT/SYNC
ROSC
SGND
fSW
2.25MHz
fSW 1/ROSC
3615 F04
LTC3615
SVIN
fSW
1/TP
VIN
RT/SYNC
SGND
TP
1.2V
0.3V
fSW
1/TP
TP
1.2V
0.3V
LTC3615
SVIN
VIN
RT/SYNC
SGND
15pF
RT
on the duty cycle of the two channels, choose the phase
difference between the channels to keep edges as far away
from each other as possible.
For example, for duty cycles of less than 40% for one
channel and more than 60% for the other channel, the
SW node edges will not coincide for 0° or 180° phase
shifts. If both channels have a duty cycle of around 50%,
a 90° phase difference would be a better choice. In cases
where the duty cycles are ~25% and ~50%, a 140° phase
shift (LTC3615-1 only) is preferable to the other phase
selections.
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔIL increases with higher VIN and decreases
with higher inductance.
ΔI
V
fL
V
L
OUT
SW
OUT
IN MAX
=
()
1
Having a lower ripple current reduces the core losses
in the inductor, the ESR losses in the output capacitors
and the output voltage ripple. A reasonable starting point
for selecting the ripple current is ΔIL = 0.3(IOUT(MAX)).
The largest ripple current occurs at the highest VIN. To
guarantee that the ripple current stays below a specied
maximum, the inductor value should be chosen according
to the following equation:
L
V
fI
V
OUT
SW
L MAX
OUT
IN MAX
=
()
Δ
1
The inductor value will also have an effect on Burst Mode
operation. The transition to low current operation begins
when the peak inductor current falls below a level set by
Figure 4. Setting the Switching Frequency
APPLICATIONS INFORMATION
of periods to settle until the frequency at SW matches the
frequency and phase of RT/SYNC.
When the external clock signal is removed, the LTC3615
needs approximately 5μs to detect the absence of the
external clock. During this time, the PLL will continue
to provide clock cycles before it is switched back to the
default frequency or selected frequency (set via the external
RT resistor).
A safe way of driving the RT/SYNC input is with an AC
coupling to the clock generator via a 15pF capacitor. The AC
couplingavoidscomplicationsiftheexternalclockgenerator
cannot provide a continuous clock signal at the time of
start-up, operation and shut down of the LTC3615.
In general, any abrupt clock frequency change of the
regulator will have an effect on the SW pin timing and
may cause equally sudden output voltage changes. This
must be taken into account in particular if the external
clock frequency is signicantly different from the internal
default of 2.25MHz.
Phase Selection
Channel 2 of the LTC3615 will operate in-phase, 180° out-
of-phase (anti-phase) or shifted by 90° from channel 1
depending on the state of the PHASE pin—low, midrail and
high, respectively. Channel 2 of LTC3615-1 will operate 180°
out-of-phase (anti-phase) with PHASE pin high or shifted
by 140° with PHASE midrail or low. Antiphase generally
reduces input voltage and current ripple. Crosstalk between
switch nodes SW1, SW2 and components or sensitive
lines connected to FBx, ITHx, RT/SYNC or SRLIM can
cause unstable switching waveforms and unexpectedly
large input and output voltage ripple.
The situation improves if rising and falling edges of the
switch nodes are timed carefully not to coincide. Depending
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