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参数资料
| 型号： | LTC3615EUF-1#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 16/32页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 3A DL 24QFN |
| 标准包装： | 91 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.6 V ~ 5.5 V |
| 输入电压： | 2.25 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 400kHz ~ 4MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 24-QFN 裸露焊盘（4x4） |
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LTC3615/LTC3615-1
APPLICATIONS INFORMATION
V IN
LTC3615
SV IN
R T /SYNC
f SW
2.25MHz
V IN
0.4V
R OSC
LTC3615
SV IN
R T /SYNC
SGND
f SW ∝ 1/R OSC
T P
V IN
1.2V
0.3V
LTC3615
SV IN
R T /SYNC
SGND
f SW
1/T P
15pF
T P
1.2V
0.3V
V IN
R T
LTC3615
SV IN f SW
R T /SYNC 1/T P
SGND
3615 F04
Figure 4. Setting the Switching Frequency
V OUT ?
Δ I L = ? OUT ? ? ?? 1 –
V IN(MAX) ? ?
V OUT ?
V OUT
L = ?? ?? ? ? 1 –
f SW ? Δ I L(MAX) ? ? ?
V IN(MAX) ? ?
ofperiodstosettleuntilthefrequencyatSWmatchesthe
frequency and phase of R T /SYNC.
When the external clock signal is removed, the LTC3615
needs approximately 5μs to detect the absence of the
external clock. During this time, the PLL will continue to
provide clock cycles before it is switched back to the de-
fault frequency or selected frequency (set via the external
R T resistor).
A safe way of driving the R T /SYNC input is with an AC
coupling to the clock generator via a 15pF capacitor. The
AC coupling avoids complications if the external clock
generator cannot provide a continuous clock signal at the
time of start-up, operation and shut down of the LTC3615.
In general, any abrupt clock frequency change of the
regulator will have an effect on the SW pin timing and
may cause equally sudden output voltage changes. This
must be taken into account in particular if the external
clock frequency is significantly different from the internal
default of 2.25MHz.
Phase Selection
Channel 2 of the LTC3615 will operate in-phase, 180°
out-of-phase (anti-phase) or shifted by 90° from chan-
nel 1 depending on the state of the PHASE pin—low,
midrail and high, respectively. Channel 2 of LTC3615-1
will operate 180° out-of-phase (anti-phase) with PHASE
pin high or shifted by 140° with PHASE midrail or low.
Antiphase generally reduces input voltage and current
ripple. Crosstalk between switch nodes SW1, SW2 and
components or sensitive lines connected to FBx, ITHx, R T /
SYNC or SRLIM can cause unstable switching waveforms
and unexpectedly large input and output voltage ripple.
The situation improves if rising and falling edges of the
switch nodes are timed carefully not to coincide. Depending
on the duty cycle of the two channels, choose the phase
difference between the channels to keep edges as far away
from each other as possible.
For example, for duty cycles of less than 40% for one
channel and more than 60% for the other channel, the
SW node edges will not coincide for 0° or 180° phase
shifts. If both channels have a duty cycle of around 50%,
a 90° phase difference would be a better choice. In cases
where the duty cycles are ~25% and ~50%, a 140° phase
shift (LTC3615-1 only) is preferable to the other phase
selections.
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ?I L increases with higher V IN and decreases
with higher inductance.
? V ? ?
?
? f SW ? L ? ?
Having a lower ripple current reduces the core losses
in the inductor, the ESR losses in the output capacitors
and the output voltage ripple. A reasonable starting point
for selecting the ripple current is ?I L = 0.3(I OUT(MAX) ).
The largest ripple current occurs at the highest V IN . To
guarantee that the ripple current stays below a specified
maximum, the inductor value should be chosen according
to the following equation:
? ? ?
?
?
The inductor value will also have an effect on Burst Mode
operation. The transition to low current operation begins
16
For more information www.linear.com/LTC3615
3615fb
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