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| 型号： | LTC3619BIDD#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 13/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ DL 10DFN |
| 标准包装： | 121 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.6 V ~ 5 V |
| 输入电压： | 2.5 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 2.25MHz |
| 电流 - 输出： | 400mA，800mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 10-DFN（3x3） |
LTC3619B
APPLICATIONS INFORMATION
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V OUT immediately shifts by an amount
equal to Δ I LOAD ? ESR, where ESR is the effective series
resistance of C OUT . Δ I LOAD also begins to charge or dis-
charge C OUT generating a feedback error signal used by the
regulator to return V OUT to its steady-state value. During
this recovery time, V OUT can be monitored for overshoot
or ringing that would indicate a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine the
phase margin. In addition, feedback capacitors (C F1 and
C F2 ) can be added to improve the high frequency response,
as shown in Figure 2. Capacitor C F provides phase lead by
creating a high frequency zero with R2 which improves
the phase margin.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Application Note 76.
In some applications, a more severe transient can be caused
by switching in loads with large (>1μF) input capacitors.
The discharged input capacitors are effectively put in paral-
lel with C OUT , causing a rapid drop in V OUT . No regulator
can deliver enough current to prevent this problem if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap? controller is designed
specifically for this purpose and usually incorporates cur-
rent limiting, short-circuit protection, and soft-starting.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
% Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four sources usually account for the losses in
LTC3619B circuits: 1) V IN quiescent current, 2) switching
losses, 3) I 2 R losses, 4) other system losses.
1. The V IN current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET
driver and control currents. V IN current results in a
small (<0.1%) loss that increases with V IN , even at
no load.
2. The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from V IN to ground. The resulting dQ/dt is a current
out of V IN that is typically much larger than the DC bias
current. In continuous mode, I GATECHG = f O (Q T + Q B ),
where Q T and Q B are the gate charges of the internal
top and bottom MOSFET switches. The gate charge
losses are proportional to V IN and thus their effects
will be more pronounced at higher supply voltages.
3. I 2 R losses are calculated from the DC resistances of
the internal switches, R SW , and external inductor, R L .
In continuous mode, the average output current flows
through inductor L, but is “chopped” between the internal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
bottom MOSFET R DS(ON) and the duty cycle (DC) as
follows:
R SW = (R DS(ON)TOP ) ? ( DC) + (R DS(ON)BOT ) ? (1– DC)
The R DS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I 2 R losses:
I 2 R losses = I OUT 2 ? ( R SW + R L )
3619bfb
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