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参数资料
| 型号： | LTC3632IMS8E#TRPBF |
| 厂商： | LINEAR INTEGRATED SYSTEMS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 0.06 A SWITCHING REGULATOR, PDSO8 |
| 封装： | LEAD FREE, PLASTIC, MSOP-8 |
| 文件页数： | 6/20页 |
| 文件大小： | 247K |
| 代理商： | LTC3632IMS8E#TRPBF |
LTC3632
14
3632f
APPLICATIONS INFORMATION
To increase the duration of the reference voltage soft-start,
place a capacitor from the SS pin to ground. An internal
5μA pull-up current will charge this capacitor, resulting in
a soft-start ramp time given by:
tC
V
μA
SS
=
.
08
5
When the LTC3632 detects a fault condition (input supply
undervoltage or overvoltage) or when the RUN pin falls
below 1.1V, the SS pin is quickly pulled to ground and the
internal soft-start timer is reset. This ensures an orderly
restart when using an external soft-start capacitor.
The duration of the 0.75ms internal peak current soft-
start may be increased by placing a capacitor from the
ISET pin to ground. The peak current soft-start will ramp
from 10mA to the nal peak current value determined by a
resistor from ISET to ground. A 1μA current is sourced out
of the ISET pin. With only a capacitor connected between
ISET and ground, the peak current ramps linearly from
10mA to 50mA, and the peak current soft-start time can
be expressed as:
tC
V
μA
SS ISET
ISET
()
.
=
08
1
A linear ramp of peak current appears as a quadratic
waveform on the output voltage. For the case where the
peak current is reduced by placing a resistor from ISET
to ground, the peak current offset ramps as a decaying
exponential with a time constant of RISET CISET. For this
case, the peak current soft-start time is approximately
3 RISET CISET.
Unlike the SS pin, the ISET pin does not get pulled to ground
during an abnormal event; however, if the ISET pin is oat-
ing (programmed to 50mA peak current), the SS and ISET
pins may be tied together and connected to a capacitor
to ground. For this special case, both the peak current
and the reference voltage will soft-start on power-up and
after fault conditions. The ramp time for this combination
is CSS(ISET) (0.8V/6μA).
Efciency Considerations
The efciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efciency and which change would produce
the most improvement. Efciency can be expressed as:
Efciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: VIN operating current and I2R losses. The VIN
operating current dominates the efciency loss at very
low load currents whereas the I2R loss dominates the
efciency loss at medium to high load currents.
1. The VIN operating current comprises two components:
The DC supply current as given in the electrical charac-
teristics and the internal MOSFET gate charge currents.
The gate charge current results from switching the gate
capacitance of the internal power MOSFET switches.
Each time the gate is switched from high to low to
high again, a packet of charge, dQ, moves from VIN to
ground. The resulting dQ/dt is the current out of VIN
that is typically larger than the DC bias current.
2. I2R losses are calculated from the resistances of the
internal switches, RSW, and external inductor RL. When
switching, the average output current owing through
the inductor is “chopped” between the high side PMOS
switch and the low side NMOS switch. Thus, the series
resistance looking back into the switch pin is a function
of the top and bottom switch RDS(ON) values and the
duty cycle (DC = VOUT/VIN) as follows:
RSW = (RDS(ON)TOP)DC + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain the I2R losses, simply add
RSW to RL and multiply the result by the square of the
average output current:
I2R Loss = IO2(RSW + RL)
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