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| 型号： | LTC3633EUFD#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 21/28页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 3A DL 28QFN |
| 标准包装： | 73 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.6 V ~ 14.7 V |
| 输入电压： | 3.6 V ~ 15 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 500kHz ~ 4MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 28-QFN（4x5） |
| 产品目录页面： | 1335 (CN2011-ZH PDF) |
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LTC3633
APPLICATIONS INFORMATION
L1 = ?
? ? 1 ?
? = 0.64 μ H
C OUT1 ≈
3 ? ?I OUT 3 ? (3A)
of power loss in the package with corresponding output
load current. Although making this measurement with this
method does violate absolute maximum voltage ratings
on the PGOOD pin, the applied power is so low that there
should be no significant risk of damaging the device.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3633. Check the following in your layout:
1) Do the input capacitors connect to the V IN and PGND
pins as close as possible? These capacitors provide
the AC current to the internal power MOSFETs and their
drivers.
2) The output capacitor, C OUT , and inductor L should be
closely connected to minimize loss. The (–) plate of
C OUT should be closely connected to both PGND and
the (–) plate of C IN .
3) The resistive divider, (e.g. R1 to R4 in Figure 8) must be
connected between the (+) plate of C OUT and a ground
line terminated near SGND. The feedback signal V FB
should be routed away from noisy components and
traces, such as the SW line, and its trace length should
be minimized. In addition, the R T resistor and loop
compensation components should be terminated to
SGND.
4) Keep sensitive components away from the SW pin. The
R T resistor, the compensation components, the feedback
resistors, and the INTV CC bypass capacitor should all
be routed away from the SW trace and the inductor L.
5) A ground plane is preferred, but if not available, the
signal and power grounds should be segregated with
both connecting to a common, low noise reference point.
The connection to the PGND pin should be made with
a minimal resistance trace from the reference point.
6) Flood all unused areas on all layers with copper in order
to reduce the temperature rise of power components.
These copper areas should be connected to the exposed
backside of the package (PGND).
Refer to Figures 9 and 10 for board layout examples.
Design Example
As a design example, consider using the LTC3633 in an
application with the following specifications: V IN(MAX) =
13.2V, V OUT1 = 1.8V, V OUT2 = 3.3V, I OUT(MAX) = 3A, I OUT(MIN)
= 10mA, f = 2MHz, V DROOP ~ (5% ? V OUT ). The following
discussion will use equations from the previous sections.
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized.
First, the correct R T resistor value for 2MHz switching fre-
quency must be chosen. Based on the equation discussed
earlier, R T should be 160k; the closest standard value is
162k. RT can be tied to INTV CC if switching frequency
accuracy is not critical.
Next, determine the channel 1 inductor value for about
40% ripple current at maximum V IN :
? 1.8V ? ? 1.8V ?
? 2MHz ? 1.2A ? ? 13.2V ?
A standard value of 0.68μH should work well here. Solving
the same equation for channel 2 results in a 1μH inductor.
C OUT will be selected based on the charge storage require-
ment. For a V DROOP of 90mV for a 3A load step:
= = 50μF
f 0 V DROOP (2MHz)(90mV)
3633fc
For more information www.linear.com/LTC3633
21
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