参数资料
型号: LTC3634IFE#TRPBF
厂商: Linear Technology
文件页数: 12/28页
文件大小: 0K
描述: IC CONV DDR DDR2 DDR3 28TSSOP
标准包装: 2,500
应用: 转换器,DDR,DDR2,DDR3
输入电压: 1.4 V ~ 15 V
输出数: 2
输出电压: 0.6 V ~ 3 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
供应商设备封装: 28-TSSOP 裸露焊盘
包装: 带卷 (TR)
LTC3634
OPERATION
R RT =
pulsestobedrawnfromtheinputcapacitorandsupply
at the same time. When running the LTC3634 channels
out-of-phase, the large current pulses are interleaved,
effectively reducing the amount of time the pulses overlap.
Thus, the total RMS input current is decreased, which both
relaxes the capacitance requirements for the V IN bypass
capacitors and reduces the voltage noise on the supply line.
One potential disadvantage to this configuration occurs
APPLICATIONS INFORMATION
A general LTC3634 application circuit is shown in Figure 1.
External component selection is largely driven by the load
requirement and switching frequency. Component selec-
tion typically begins with selecting the feedback resistors
to set the desired output voltage. Next the inductor L and
resistor R T are selected. Once the inductor is chosen, the
input capacitor (C IN ) and the output capacitor (C OUT ) can
be selected. Finally, the loop compensation components
may be selected to stabilize the step-down regulator. The
remaining optional external components can then be se-
lected for functions such as loop compensation, TRACKSS,
V IN , UVLO, and PGOOD.
when one channel is operating at 50% duty cycle. In this
situation, SW node transitions can potentially couple from
one channel to the other, resulting in frequency jitter on
one or both channels. This effect can be mitigated with a
well designed board layout. Alternatively, tying PHMODE
low changes the phase difference to be 90°, which may
prevent SW1 and SW2 from transitioning at the same
point in time.
Programming Switching Frequency
Selection of the switching frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but generally requires
larger inductance and capacitance values to maintain low
output ripple voltage. Connecting a resistor from the RT
pin to SGND programs the switching frequency (f) between
500kHz and 4MHz according to the following formula:
3.2E 11
f
where R RT is in Ω and f is in Hz.
V IN
3.6V TO 15V
C1
RUN1
V IN2
V IN1
BOOST1
RUN2
RT
LTC3634
SW1
0.1μF
L1
V DDQ
R RT
C2
2.2μF
INTV CC
PHMODE
MODE/SYNC
V ON1
VDDQIN
V FB1
R2
C OUT1
ITH1
BOOST2
R1
R COMP1
C COMP1
C4
(OPT)
SW2
V FB2
0.1μF
L2
V TT
R COMP2
C5
(OPT)
ITH2
SGND
PGND
V ON2
VTTR
3634 F01
V REF
C3
0.01μF
C OUT2
C COMP2
Figure 1. Typical Application Circuit for DDR Memory Supply
3634fb
12
For more information www.linear.com/LTC3634
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