参数资料
型号: LTC3733CG
厂商: Linear Technology
文件页数: 23/32页
文件大小: 0K
描述: IC CTRLR BUCK AMD 3PHASE 36-SSOP
标准包装: 37
应用: 控制器,AMD
输入电压: 4 V ~ 36 V
输出数: 1
输出电压: 0.8 V ~ 1.55 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 36-SSOP(0.209",5.30mm 宽)
供应商设备封装: 36-SSOP
包装: 管件
产品目录页面: 1339 (CN2011-ZH PDF)
LTC3733/LTC3733-1
APPLICATIO S I FOR ATIO
The I TH series R C -C C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to maximize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 80% of full load current having a rise time
of <2 μ s will produce output voltage and I TH pin waveforms
R SENSE resistor would require a 500 μ s rise time, limiting
the charging current to about 1A.
Design Example (Using Three Phases)
As a design example, assume V IN = 12V(nominal), V IN =
20V(max), V OUT = 1.3V, I MAX = 45A and f = 400kHz. The
inductance value is chosen first based upon a 30% ripple
current assumption. The highest value of ripple current in
each output stage occurs at the maximum input voltage.
? 1 ?
V OUT ? V OUT ?
f ( ) I ?
V IN ?
?
that will give a sense of the overall loop stability without
breaking the feedback loop. The initial output voltage step,
resulting from the step change in output current, may not
L =
?
? 1 ?
=
?
bewithinthebandwidthofthefeedbackloop,sothissignal
cannot be used to determine phase margin. This is why it
is better to look at the I TH pin signal which is in the
feedback loop and is the filtered and compensated control
1 . 3 V ?
( 400 kHz )( 30 % )( 15 A ) ?
≥ 0 . 68 μ H
1 . 3 V ?
20 V ?
loop response. The gain of the loop will be increased by
increasing R C and the bandwidth of the loop will be
increased by decreasing C C . If R C is increased by the same
factor that C C is decreased, the zero frequency will be kept
the same, thereby keeping the phase the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual over-
all supply performance.
Using L = 0.6 μ H, a commonly available value results in
34% ripple current. The worst-case output ripple for the
three stages operating in parallel will be less than 11% of
the peak output current.
R SENSE1, R SENSE2 and R SENSE3 can be calculated by using
a conservative maximum sense current threshold of 65mV
and taking into account half of the ripple current:
15 A ? 1 +
?
Asecond,moreseveretransientiscausedbyswitchingin
loads with large (>1 μ F) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
R SENSE =
65 mV
? 34 % ?
? 2 ?
= 0 . 0037 ?
with C OUT , causing a rapid drop in V OUT . No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If C LOAD is greater
Use a commonly available 0.003 ? sense resistor.
Next verify the minimum on-time is not violated. The
minimum on-time occurs at maximum V CC :
than 2% of C OUT , the switch rise time should be controlled
so that the load rise time is limited to approximately
1000 ? R SENSE ? C LOAD . Thus a 250 μ F capacitor and a 2m ?
t ON ( MIN ) =
V OUT
V IN ( MAX ) ( f )
=
1 . 3 V
20 V ( 400 kHz )
= 162 ns
3733f
23
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