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参数资料
| 型号： | LTC3733CUHF-1#TR |
| 厂商： | Linear Technology |
| 文件页数： | 8/32页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK 3PH AMD CPU 38-QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，AMD |
| 输入电压： | 4 V ~ 36 V |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 1.55 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-WFQFN 裸露焊盘 |
| 供应商设备封装： | 38-QFN（5x7） |
| 包装： | 带卷 (TR) |
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LTC3733/LTC3733-1
PI FU CTIO S
(G36/QFN)
VID0 to VID4 (Pins 36, 1, 18, 19, 20/Pins 35, 36, 16, 17,
18): Output Voltage Programming Input Pins. A 150k
internal pull-up resistor is provided on each input pin. See
Table 1 for details. Do not apply voltage to these pins prior
to the application of voltage on the V CC pin.
RUN (Pin 2/Pin 37): ON/OFF Control of the LTC3733.
PLLFLTR (Pin 3/Pin 1): The phase-locked loop’s lowpass
filter is tied to this pin. Alternatively, this pin can be driven
with an AC or DC voltage source to vary the frequency of
the internal oscillator. (Do not apply voltage to this pin
prior to the application of voltage on the V CC pin.)
FCB (Pin 4/Pin 2): Forced Continuous Control Input. The
voltage applied to this pin sets the operating mode of the
controller. The forced continuous current mode is active
when the applied voltage is less than 0.6V. Burst Mode
operation will be active when the pin is allowed to float and
a stage shedding mode will be active if the pin is tied to the
V CC pin. (Do not apply voltage to this pin prior to the
application of voltage on the V CC pin.)
IN + , IN – (Pins 5, 6/Pins 3, 4): Inputs to a precision, unity-
gain differential amplifier with internal precision resistors.
This provides true remote sensing of both the positive and
negative load terminals for precise output voltage control.
DIFFOUT (Pin 7/Pin 5): Output of the Remote Output
Voltage Sensing Differential Amplifier.
EAIN (Pin 8/Pin 6): This is the input to the error amplifier
which compares the VID divided, feedback voltage to the
internal 0.6V reference voltage.
SGND (Pin 9/Pin 7, 39): Signal Ground. This pin must be
routed separately under the IC to the PGND pin and then
to the main ground plane. The exposed pad (QFN) must be
soldered to the PCB for optimal thermal performance.
SENSE1 + , SENSE2 + , SENSE3 + , SENSE1 – , SENSE2 – ,
SENSE3 – (Pins 10 to 15/Pins 8 to 13): The Inputs to Each
Differential Current Comparator. The I TH pin voltage and
built-in offsets between SENSE – and SENSE + pins, in con-
junction with R SENSE , set the current trip threshold level.
SS (Pin 16/Pin 14): Combination of Soft-Start and Short-
Circuit Detection Timer. A capacitor to ground at this pin
sets the ramp time to full current output as well as the time
delay prior to an output voltage short-circuit shutdown. A
minimum value of 0.01 μ F is recommended on this pin.
I TH (Pin 17/Pin 15): Error Amplifier Output and Switching
Regulator Compensation Point. All three current
comparator’s thresholds increase with this control voltage.
PGND (Pin 26/Pin 24): Driver Power Ground. This pin
connects to the sources of the bottom N-channel external
MOSFETs and the (–) terminals of C IN .
BG1 to BG3 (Pins 27, 25, 24/Pins 25, 23, 22): High
Current Gate Drives for Bottom N-Channel MOSFETs.
Voltage swing at these pins is from ground to V CC .
DRV CC (NA/Pin 26): High Power Supply to Drive the
External MOSFET Gates in QFN Package. This pin needs to
be closely decoupled to the IC’s PGND pin.
V CC (Pin 28/Pin 27): Main Supply Pin. This pin supplies
the controller circuit power. In the G36 package, it is also
the high power supply to drive the external MOSFET gates
and this pin needs to be closely decoupled to the IC’s
PGND pin.
SW1 to SW3 (Pins 32, 29, 23/Pins 31, 28, 21): Switch
Node Connections to Inductors. Voltage swing at these
pins is from a Schottky diode (external) voltage drop
below ground to V IN (where V IN is the external MOSFET
supply rail).
3733f
8
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