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参数资料
| 型号： | LTC3735EUHF#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 11/32页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR DC/DC 2PH HI EFF 38-QFN |
| 标准包装： | 52 |
| 应用： | 控制器，Intel 移动式 CPU |
| 输出数： | 1 |
| 输出电压： | 0.7 V ~ 1.71 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-WFQFN 裸露焊盘 |
| 供应商设备封装： | 38-QFN（5x7） |
| 包装： | 管件 |
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LTC3735
OPERATION
(Refer to Functional Diagram)
Output Voltage at Start-Up and at Deeper Sleep State
Under normal conditions, the output voltage of the regula-
tor is commanded by six VID bits, except at start-up and
at deeper sleep state. At start-up, the RUN/SS capacitor
starts to charge up and its voltage limits the inrush current
from the input power source. This linearly rising current
limit provides a controlled output voltage rise. During
start-up, the VID command is ignored and the output set
point is determined by the value of the resistor connected
to the RBOOT pin. The VID bits continue to be ignored for
15 switching cycles after the completion of the following
two conditions: 1) output voltage has risen up and has
regulated 2) MCH_PG signal has asserted. After 15 switch-
ing cycles, output voltage is fully commanded by VID bits.
In deeper sleep state, the VID command and STP_CPUB
signal are ignored and the output set point is determined
by the parallel value of the resistors at the RDPRSLP pin
and RDPSLP pin.
Operational Amplifier and Deep Sleep Offset
The internal operational amplifier provides a programmable
output offset at deep sleep state (when the STP_CPUB
signal is low). The offset percentage is programmed by
the resistor from RDPSLP to V OA+ and the resistor from
output to V OA+ . The amplifier has an output slew rate of
5V/μs and is capable of driving capacitive loads with an
output RMS current typically up to 40mA. The open-loop
gain of the amplifier is >120dB and the unity-gain band-
width is 2MHz.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious condi-
tions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Power Good
The PGOOD pin is connected to the drain of an internal
N-channel MOSFET. The MOSFET turns on when the out-
put voltage is not within ±10% of its nominal set point.
When the output voltage is within ±10% of its nominal set
point, the MOSFET turns off and PGOOD is high imped-
ance. PGOOD monitors the V BOOT voltage when MCH_PG
is not asserted. During VID, deep sleep or deeper sleep
transitions, PGOOD is masked from going low for 110μs,
preventing the system from resetting during CPU mode
changes. When VID bits, STP_CPUB or DPRSLPVR signals
change again after a previous transition, but before the
timer expires, the internal timer resets.
Short-Circuit Detection
The RUN/SS capacitor is used initially to limit the in-
rush current from the input power source. Once the
controllers have been given time, as determined by the
capacitor on the RUN/SS pin, to charge up the output
capacitors and provide full-load current, the RUN/SS
capacitor is then used as a short-circuit timeout circuit.
If the output voltage falls to less than 70% of its nominal
output voltage the RUN/SS capacitor begins discharg-
ing assuming that the output is in a severe overcurrent
and/or short-circuit condition. If the condition lasts for
a long enough period as determined by the size of the
RUN/SS capacitor, the controller will be shut down until the
RUN/SS pin voltage is recycled. This built-in latchoff can
be overidden by providing a current >5μA to the RUN/SS
pin. This current shortens the soft-start period but also
prevents net discharge of the RUN/SS capacitor during a
severe overcurrent and/or short-circuit condition. Foldback
current limiting is activated when the output voltage falls
below 70% of its nominal level whether or not the short-
circuit latchoff circuit is enabled.
3735fa
11
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