参数资料
型号: LTC3736-2EUF#TRPBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 稳压器
英文描述: SWITCHING CONTROLLER, PQCC24
封装: 4 X 4 MM, LEAD FREE, PLASTIC, QFN-24
文件页数: 11/28页
文件大小: 344K
代理商: LTC3736-2EUF#TRPBF
LTC3736-2
19
37362fb
APPLICATIONS INFORMATION
For coincident tracking,
tt
V
SS
OUT F
21
2
1
=
where VOUT1F and VOUT2F are the nal, regulated values
of VOUT1 and VOUT2. VOUT1 should always be greater than
VOUT2 when using the TRACK pin. If no tracking function is
desired, then the TRACK pin may be tied to VIN. However,
in this situation there would be no (internal nor external)
soft-start on VOUT2.
Phase-Locked Loop and Frequency Synchronization
The LTC3736-2 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the external P-channel
MOSFET of controller 1 to be locked to the rising edge
of an external clock signal applied to the SYNC/FCB pin.
The turn-on of controller 2’s external P-channel MOSFET
is thus 180 degrees out-of-phase with the external clock.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the external lter
network connected to the PLLLPF pin. The relationship
between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to SYNC/
FCB, is shown in Figure 8 and specied in the Electrical
Characteristics table. Note that the LTC3736-2 can only be
synchronized to an external clock whose frequency is within
range of the LTC3736-2’s internal VCO, which is nominally
200kHz to 1MHz. This is guaranteed, over temperature and
variations, to be between 300kHz and 750kHz. A simplied
block diagram is shown in Figure 9.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
Figures 7b and 7c. Two Different Modes of Output Voltage Tracking
TIME
(7b) Coincident Tracking
VOUT1
VOUT2
OUTPUT
VOL
TAGE
TIME
37362 F07b,c
(7c) Ratiometric Tracking
VOUT1
VOUT2
OUTPUT
VOL
TAGE
Figure 8. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
PLLLPF PIN VOLTAGE (V)
0
FREQUENCY
(kHz)
0.5
1
1.5
2
37362 F08
2.4
200
400
600
800
1000
1200
1400
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