参数资料
型号: LTC3780EG#PBF
厂商: Linear Technology
文件页数: 24/30页
文件大小: 0K
描述: IC REG CTRLR BST PWM CM 24-SSOP
标准包装: 59
PWM 型: 电流模式
输出数: 1
频率 - 最大: 440kHz
占空比: 99%
电源电压: 4 V ~ 36 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-SSOP(0.209",5.30mm 宽)
包装: 管件
产品目录页面: 1336 (CN2011-ZH PDF)
LTC3780
APPLICATIONS INFORMATION
I IN , PEAK ( MAX , BUCK ) = 5 ? ? 1 +
? 29 % ?
2 ? ?
?
Double-check the T J in the MOSFET with 70°C ambient
temperature:
T J = 70°C + 1.94W ? 40°C/W = 147.6°C
The maximum power dissipation of switch B occurs in
buck mode. Assuming a junction temperature of T J = 80°C
with ρ 80°C = 1.2, the power dissipation at V IN = 18V is:
C IN is chosen to filter the square current in buck mode. In
this mode, the maximum input current peak is:
= 5 . 7 A
A low ESR (10mΩ) capacitor is selected. Input voltage
ripple is 57mV (assuming ESR dominate ripple).
P B,BUCK =
18 – 12
18
? 5 2 ? 1.2 ? 0.009 = 90mW
C OUT is chosen to filter the square current in boost mode.
In this mode, the maximum output current peak is:
? 5 ? ? 1 +
Double-check the T J in the MOSFET at 70°C ambient
temperature:
I OUT , PEAK ( MAX , BOOST ) =
12
5
?
?
11 % ?
2 ? ?
= 10 . 6 A
P C,BOOST = ( 12 – 5 ) ? 12 ? 5 2 ? 1.4 ? 0.009
+ 2 ? 12 3 ? ? 150p ? 400k = 1.27W
T J = 70°C + 0.09W ? 40°C/W = 73.6°C
The maximum power dissipation of switch C occurs in boost
mode. Assuming a junction temperature of T J = 110°C with
ρ 110°C = 1.4, the power dissipation at V IN = 5V is:
5 2
5
5
Double-check the T J in the MOSFET at 70°C ambient
temperature:
T J = 70°C + 1.08W ? 40°C/W = 113°C
The maximum power dissipation of switch D occurs
in boost mode when its duty cycle is higher than 50%.
Assuming a junction temperature of T J = 100°C with
ρ 100°C = 1.35, the power dissipation at V IN = 5V is:
A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 53mV (assuming ESR
dominate ripple).
PC Board Layout Checklist
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
? The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
? Place C IN , switch A, switch B and D1 in one com-
pact area. Place C OUT , switch C, switch D and D2 in
one compact area. One layout example is shown in
Figure 10.
5 ? 12
?
P D , BOOST = ? ? ? 5 ? ? 1 . 35 ? 0 . 009 = 0 . 73 W
2
12 ? 5 ?
Double-check the T J in the MOSFET at 70°C ambient
temperature:
T J = 70°C + 0.73W ? 40°C/W = 99°C
V IN
C IN
QA
D1
SW2
QB
L
SW1
QC
D2
QD
V OUT
C OUT
R SENSE
LTC3780
CKT
GND
3780 F10
Figure 10. Switches Layout
3780ff
24
For more information www.linear.com/LTC3780
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