参数资料
型号: LTC3789EUFD#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 稳压器
英文描述: 0.1 A SWITCHING CONTROLLER, 710 kHz SWITCHING FREQ-MAX, PQCC28
封装: 4 X 5 MM, LEAD FREE, PLASTIC, MO-220, QFN-28
文件页数: 16/28页
文件大小: 486K
代理商: LTC3789EUFD#PBF
LTC3789
23
3789f
applicaTions inForMaTion
The Vishay SiR422DP has a typical RDS(ON) of 0.010Ω at
TJ = 125°C and VGS = 4.5V.
The maximum dissipation in QB occurs at maximum input
voltage when the circuit is operating in the buck region.
The dissipation is:
PB,BUCK =
VIN VOUT
VIN
IOUT(MAX)
2 ρt RDS(ON)
RDS(ON)(125°C) <
1.3W
18V TO 12V
18V
(5A)2
= 0.156
This seems to indicate that a quite small MOSFET can be
used for QB if we only look at power loss. However, with
5A current the voltage drop across 0.156Ω is 0.78V, which
meanstheMOSFETbodydiodeisconducting.Toavoidbody
diode current flow we should keep the maximum voltage
dropwellbelow0.5V,using,forexample,VishaySi4840BDY
in the SO-8 package (RDSON(MAX) = 0.012Ω).
Select QC and QD. With 12V output voltage we need
MOSFETs with 20V or higher rating.
The highest dissipation occurs at minimum input voltage
when the inductor current is highest. For switch QC the
dissipation is:
PC,BOOST =
(VOUT VIN)VOUT
VIN 2
IOUT(MAX)2 ρt RDS(ON)
+ k VOUT3
IOUT(MAX)
VIN
CRSS f
whereCRSSisusuallyspecifiedbytheMOSFETmanufactur-
ers. The constant k, which accounts for the loss caused by
reverse recovery current, is inversely proportional to the
gate drive current and has an empirical value of 1.7.
The dissipation in switch QD is:
PD,BOOST =
VIN
VOUT
VOUT
VIN
IOUT(MAX)
2
ρt RDS(ON)
Vishay SiR484OY is a possible choice for QC and QD. The
calculated power loss at 5V input voltage is then 1.3W for
QC and 0.84W for QD.
CINischosentofilterthesquarecurrentinthebuckregion.
In this mode, the maximum input current peak is:
IIN,PEAK(MAX,BUCK) = 5A 1+
29%
2
= 5.7A
A low ESR (10mΩ) capacitor is selected. Input voltage
ripple is 57mV (assuming ESR dominates the ripple).
COUT is chosen to filter the square current in the boost
region. In this mode, the maximum output current peak is:
IOUT,PEAK(MAX,BOOST) =
12
5
5 1+ 11%
2
= 10.6A
A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 53mV (assuming ESR
dominates the ripple).
PC Board Layout Checklist
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
The ground plane layer should not have any traces and
should be as close as possible to the layer with power
MOSFETs.
Place CIN, switch A, switch B and D1 in one com-
pact area. Place COUT, switch C, switch D and D2 in
one compact area. One layout example is shown in
Figure 12.
Use immediate vias to connect the components (in-
cluding the LTC3789’s SGND and PGND pins) to the
ground plane. Use several large vias for each power
component.
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相关代理商/技术参数
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