参数资料
型号: LTC3789EUFD#TRPBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 稳压器
英文描述: 0.1 A SWITCHING CONTROLLER, 710 kHz SWITCHING FREQ-MAX, PQCC28
封装: 4 X 5 MM, LEAD FREE, PLASTIC, MO-220, QFN-28
文件页数: 8/28页
文件大小: 486K
代理商: LTC3789EUFD#TRPBF
LTC3789
16
3789f
applicaTions inForMaTion
With the typical 100Ω resistors shown here, the value of
capacitor CF should be 1F to 2.2F. The current loop’s
transfer function should approximate that of the voltage
loop.Crossoverfrequencyshouldbeone-tenththeswitch-
ing frequency, and gain should decrease by 20dB/decade.
Similar current and voltage loop transfer functions will
ensure overall system stability.
When the IOSENSE common mode voltage is above ~3.2V,
the IOSENSE– pin sources 10A. The IOSENSE+ pin, however,
sources 18.3A, 26.6A and 35A when the ILIM pin is
low, floating, and high, respectively, and when a constant
current is being regulated. The error introduced by this
mismatch can be offset to a first order by scaling the
IOSENSE+ and IOSENSE– resistors accordingly. For example,
if the IOSENSE+ branch has a 100Ω resistor, the 1.83mV
across it can be replicated in the IOSENSE– branch by using
a 182Ω resistor.
WhentheIOSENSEcommonmodevoltagefallsbelow~3.2V
by a diode drop, the IOSENSE current decreases linearly; it
reaches approximately –300A at zero volts. The values
of the diode drop and maximum current sinking can vary
by 20% to 30% due to process variation.
Slope Compensation
Slope compensation provides stability in constant-
frequency architectures by preventing subharmonic
oscillations at high duty cycles in boost operation and at
low duty cycles in buck operation. This is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40% in the boost
region, or subtracting a ramp from the inductor current
signal at lower than 40% duty cycles in the buck region.
Normally, this results in a reduction of maximum inductor
peak current for duty cycles >40% in the boost region, or
an increase of maximum inductor current for duty cycles
<40% in the buck region. However, the LTC3789 uses a
scheme that counteracts this compensating ramp, which
allowsthemaximuminductorcurrenttoremainunaffected
throughout all duty cycles.
Phase-Locked Loop and Frequency Synchronization
The LTC3789 has a phase-locked loop (PLL) comprised of
aninternalvoltage-controlledoscillator(VCO)andaphase
detector. This allows the turn-on of the top MOSFET of the
controller to be locked to the rising edge of an external
clock signal applied to the MODE/PLLIN pin. The phase
detector is an edge sensitive digital type that provides
zero degrees phase shift between the external and internal
oscillators. This type of phase detector does not exhibit
false locking to harmonics of the external clock.
The output of the phase detector is a pair of comple-
mentary current sources that charge or discharge the
internal filter network. There is a precision 10A of cur-
rent flowing out of the FREQ pin. This allows a single
resistor to SGND to set the switching frequency when
no external clock is applied to the MODE/PLLIN pin. The
internal switch between FREQ and the integrated PLL filter
network is on, allowing the filter network to be at the same
voltage on the FREQ pin. Operating frequency is shown
in Figure 9 and specified in the Electrical Characteristics
table. If an external clock is detected on the MODE/PLLIN
pin, the internal switch previously mentioned will turn
off and isolate the influence of the FREQ pin. Note that
the LTC3789 can only be synchronized to an external
FREQ PIN VOLTAGE (V)
0
FREQUENCY
(kHz)
0.5
1
1.5
2
3789 F09
2.5
0
100
300
400
500
800
700
200
600
Figure 9. Relationship Between Oscillator
Frequency and Voltage at the FREQ Pin
相关PDF资料
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