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参数资料
| 型号： | LTC3802EGN#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 28-SSOP |
| 标准包装： | 2,500 |
| 系列： | PolyPhase® |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 850kHz |
| 占空比： | 92% |
| 电源电压： | 3 V ~ 30 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-SSOP（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
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LTC3802
APPLICATIO S I FOR ATIO
special power supplies with a slow start-up slew rate, the
LTC3802 drivers might start switching before the input
supply reaches its steady-state value. The high inrush
current through the input power cable might cause the V IN
supply to dip below the UVLO threshold and cause start-
up problems. Figure 3 shows a simple circuit to fix this
problem. The selection of the zener voltage allows the V IN
UVLO trip point to be programmed externally.
The LTC3802 can be configured to give two different
power-up/power-down slew rates to meet different appli-
cation requirements: ratiometric and coincident tracking
configurations (Figure 4). With a ratiometric configura-
tion, the LTC3802 produces two different output slew
rates (with V OUT1 > V OUT2 ). Because each channel’s slew
rate is proportional to its corresponding output voltage,
the two output voltages reach their steady-state value at
about the same time. The coincident configuration pro-
duces the same slew rate at both outputs, so that the lower
V IN > V Z
LTC3802
output voltage channel reaches its steady state first.
1N4699
V Z = 12V
100k
10k
100k
Q1
2N3904
Q2
2N3904
C SS
RUN/SS
Figure 4 shows the simplified schematic to realize this
power-up function. During power-up, the tracking ampli-
fier TRACK servos the tracking feedback loop and forces
3802 F03
Figure 3. External UVLO Setting
Start-Up Tracking
Many DSP chips, microprocessors, FPGAs and ASICs
require multiple power supplies for the core and I/O
sections. Internally, the core and I/O blocks are isolated by
structures which may become forward biased if the supply
voltages are not at specified levels. During power-up and
power-down operations, differences in the starting point
and ramp rates of the two supplies may cause current to
flow between the isolation structures which, when pro-
longed and excessive, can reduce the useable life of the
semiconductor device. These currents can also trigger
latch-up in devices, leading to device failure.
Of greater concern than internal isolation of core and I/O
structures are system-level concerns, such as bus
contention between the I/O pins of the DSP and external
peripheral devices. Power supply sequencing between the
core and I/O may be required to prevent bidirectional I/O
pins of the DSP and a peripheral device from opposing
each other. Since the bus control logic originates in the
core section, powering the I/O prior to the core may cause
the DSP and peripheral pins to be configured
simulatneously as outputs. If the data values on each side
are opposing, then the output drivers contend for control,
causing excessive current flow and eventually device
failure.
FBT to be at the same potential as CMPIN2.
For ratiometric start-up, set:
R T5 = R51
or remove resistors R T4 and R T5 and short FBT to CMPIN1.
At power-up, if the channel 2 output voltage slew rate is
too fast, or CMPIN2 is higher than FBT, the tracking
amplifier will force a smaller channel 2 duty cycle.
Channel 1’s duty cycle is controlled by the RUN/SS pin and
is not affected by the tracking amplifier.
For coincident start-up, set:
R T5 = R52
During power-up, if the channel 1 output voltage is higher
than that of channel 2, or if FBT is higher than CMPIN2, the
tracking amplifier TRACK starts to discharge the C SS
capacitor and forces both channels to have the same duty
cycle and output voltage. The tracking amplifier stops
discharging once channel 2 reaches its negative power
good threshold.
To have the proper power-down sequence, ground the
PHASEMD pin. This turns on an internal current source
which slowly discharges the soft-start capacitor. Once the
RUN/SS potential is low enough to control the duty cycle,
the tracking amplifier takes control and servos the feed-
back loop to produce the selected output ramp. The
LTC3802 tracking function can be easily disabled by
disconnecting the FBT resistive divider and shorting FBT
to CMPIN2.
3802f
17
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC3802EUH | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:PolyPhase® 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| LTC3802EUH#PBF | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:PolyPhase® 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| LTC3802EUH#TR | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:PolyPhase® 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| LTC3802EUH#TRPBF | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:PolyPhase® 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| LTC3803ES6 | 制造商:Linear Technology 功能描述:DC DC Cntrlr Single-OUT Flyback Controller 9.2V to 75V Input 6-Pin TSOT-23 |
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