参数资料
型号: LTC3808EGN#TRPBF
厂商: Linear Technology
文件页数: 11/28页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 16-SSOP
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 825kHz
占空比: 100%
电源电压: 2.75 V ~ 9.8 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
包装: 带卷 (TR)
LTC3808
OPERATIO
(Refer to Functional Diagram)
A phase-locked loop (PLL) is available on the LTC3808 to
synchronize the internal oscillator to an external clock
source that connects to the SYNC/MODE pin. In this case,
a series RC should be connected between the PLLLPF pin
and GND to serve as the PLL’s loop filter. The LTC3808
phase detector adjusts the voltage on the PLLLPF pin to
align the turn-on of the external P-channel MOSFET to the
rising edge of the synchronizing signal.
The typical capture range of the LTC3808’s phase-locked
loop is from approximately 200kHz to 1MHz.
Spread Spectrum Modulation (SYNC/MODE and
PLLLPF Pins)
Connecting the SYNC/MODE pin to a DC voltage above
1.35V and several hundred mV below V IN enables spread
spectrum modulation (SSM) operation. An internal 2.6 μ A
pull-down current source at SYNC/MODE helps to set the
voltage at the SYNC/MODE pin for this operation by tying
a resistor with appropriate value between SYNC/MODE
and V IN . This mode of operation spreads the internal
oscillator frequency f OSC (= 550kHz) over a wider range
(460kHz to 635kHz), reducing the peaks of the harmonic
output on a spectral analysis of the output noise. In this
case, a 2.2nF filter cap should be connected between the
PLLLPF pin and GND and another 1000pF cap should be
connected between PLLLPF and the SYNC/MODE pin. The
controller operates in PWM pulse skipping mode at light
loads when spread spectrum modulation is selected. See
more discussions in the Spread Spectrum Modulation
with SYNC/MODE and PLLLPF Pins in the Applications
Dropout Operation
When the input supply voltage (V IN ) approaches the
output voltage, the rate of change of the inductor current
while the external P-channel MOSFET is on
(ON cycle) decreases. This reduction means that the
P-channel MOSFET will remain on for more than one
oscillator cycle if the inductor current has not ramped up
to the threshold set by the EAMP on the I TH pin. Further
reduction in the input supply voltage will eventually cause
the P-channel MOSFET to be turned on 100%; i.e., DC.
The output voltage will then be determined by the input
voltage minus the voltage drop across the P-channel
MOSFET and the inductor.
Undervoltage Lockout
To prevent operation of the P-channel MOSFET below
safe input voltage levels, an undervoltage lockout is
incorporated in the LTC3808. When the input supply
voltage (V IN ) drops below 2.25V, the external P- and
N-channel MOSFETs and all internal circuits are turned
off except for the undervoltage block, which draws only
a few microamperes.
Peak Current Sense Voltage Selection and Slope
Compensation (IPRG Pin)
When the LTC3808 controller is operating below 20% duty
cycle, the peak current sense voltage (between the SENSE +
and SENSE – /SW pins) allowed across the external P-
channel MOSFET is determined by:
Information section.
? V SENSE ( MAX ) = A ?
V ITH – 0.7 V
10
where A is a constant determined by the state of the IPRG
pin. Floating the IPRG pin selects A = 1; tying IPRG to V IN
selects A = 5/3; tying IPRG to GND selects A = 2/3. The
3808f
11
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