参数资料
型号: LTC3812EFE-5#PBF
厂商: Linear Technology
文件页数: 15/34页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 16TSSOP
标准包装: 95
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1MHz
占空比: 93%
电源电压: 6.2 V ~ 60 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
产品目录页面: 1336 (CN2011-ZH PDF)
LTC3812-5
APPLICATIONS INFORMATION
The most important parameter in high voltage applications
is breakdown voltage BV DSS . Both the top and bottom
MOSFETs will see full input voltage plus any additional
ringing on the switch node across its drain-to-source dur-
ing its off-time and must be chosen with the appropriate
breakdown speci?cation. The LTC3812-5 is designed to
be used with a 4.5V to 14V gate drive supply (INTV CC pin)
for driving logic-level MOSFETs (V GS(MIN) ≥ 4.5V).
For maximum ef?ciency, on-resistance R DS(ON) and input
capacitance should be minimized. Low R DS(ON) minimizes
conduction losses and low input capacitance minimizes
transition losses. MOSFET input capacitance is a combi-
voltage, but can be adjusted for different V DS voltages by
multiplying by the ratio of the application V DS to the curve
speci?ed V DS values. A way to estimate the C MILLER term
is to take the change in gate charge from points a and b
on a manufacturers data sheet and divide by the stated
V DS voltage speci?ed. C MILLER is the most important se-
lection criteria for determining the transition loss term in
the top MOSFET but is not directly speci?ed on MOSFET
data sheets. C RSS and C OS are speci?ed sometimes but
de?nitions of these parameters are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
nation of several components but can be taken from the
typical “gate charge” curve included on most data sheets
(Figure 6).
Main Switch Duty Cycle =
V OUT
V IN
V IN
Synchronous Switch Duty Cycle =
V IN – V OUT
V IN
V GS
MILLER EFFECT
V
The power dissipation for the main and synchronous
( I MAX ) 2 ( T )R DS(ON) +
P TOP =
a                             b
Q IN
C MILLER = (Q B – Q A )/V DS
+
V GS
+ V DS
38125 F06
MOSFETs at maximum output current are given by:
V OUT
V IN
V IN2 MAX (R DR )(C MILLER ) ?
Figure 6. Gate Charge Characteristic
I
2
The curve is generated by forcing a constant input cur-
rent into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
1
V CC – V TH(IL)
+
1
V TH(IL)
(f)
(I MAX ) 2 (
P BOT =
T )R DS(0N)
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The ?at portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is ?at) is speci?ed for a given V DS drain
V IN – V OUT
V IN
where ρ T is the temperature dependency of R DS(ON) , R DR
is the effective top driver resistance (approximately 2Ω at
V GS = V MILLER ), V IN is the drain potential and the change
in drain potential in the particular application. V TH(IL) is
the data sheet speci?ed typical gate threshold voltage
speci?ed in the power MOSFET data sheet at the speci?ed
38125fc
15
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