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| 型号： | LTC3814IFE-5#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 12/30页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST PWM CM 16-TSSOP |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 90% |
| 电源电压： | 4.5 V ~ 55 V |
| 降压： | 无 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 带卷 (TR) |
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LTC3814-5
APPLICATIONS INFORMATION
Power MOSFET Selection
The LTC3814-5 requires two external N-channel power
MOSFETs, one for the bottom (main) switch and one for
the top (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage BV DSS ,
threshold voltage V (GS)TH , on-resistance R DS(ON) , Miller
capacitance and maximum current I DS(MAX) .
Since the bottom MOSFET is used as the current sense
element, particular attention must be paid to its on-resis-
tance. MOSFET on-resistance is typically speci?ed with
a maximum value R DS(ON)(MAX) at 25°C. In this case,
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
ing its off-time and must be chosen with the appropriate
breakdown speci?cation. The LTC3814-5 is designed to
be used with a 4.5V to 14V gate drive supply (INTV CC pin)
for driving logic-level MOSFETs (V GS(MIN) ≥ 4.5V).
For maximum ef?ciency, on-resistance R DS(ON) and input
capacitance should be minimized. Low R DS(ON) minimizes
conduction losses and low input capacitance minimizes
transition losses. MOSFET input capacitance is a combi-
nation of several components but can be taken from the
typical “gate charge” curve included on most data sheets
(Figure 3).
V OUT
R DS(ON)(MAX) = SENSE
R
ρ T
The ρ T term is a normalization factor (unity at 25°C)
V GS
MILLER EFFECT
a b
Q IN
C MILLER = (Q B – Q A )/V DS
V
+
V GS
–
+ V
–
DS
accounting for the signi?cant variation in on-resistance
with temperature (see Figure 2) and typically varies
from 0.4%/°C to 1.0%/°C depending on the particular
MOSFET used.
2.0
1.5
1.0
0.5
38145 F03
Figure 3. Gate Charge Characteristic
The curve is generated by forcing a constant input cur-
rent into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The ?at portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is ?at) is speci?ed for a given V DS drain
0
–50
0 50 100
JUNCTION TEMPERATURE (°C)
150
38145 F02
voltage, but can be adjusted for different V DS voltages by
multiplying by the ratio of the application V DS to the curve
speci?ed V DS values. A way to estimate the C MILLER term
Figure 2. R DS(ON) vs Temperature
The most important parameter in high voltage applications
is breakdown voltage BV DSS . Both the top and bottom
MOSFETs will see full output voltage plus any additional
ringing on the switch node across its drain-to-source dur-
is to take the change in gate charge from points a and b
on a manufacturers data sheet and divide by the stated
V DS voltage speci?ed. C MILLER is the most important se-
lection criteria for determining the transition loss term in
the top MOSFET but is not directly speci?ed on MOSFET
data sheets. C RSS and C OS are speci?ed sometimes but
de?nitions of these parameters are not included.
38145fc
12
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