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参数资料
| 型号： | LTC3826IUH#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 23/36页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 32-QFN |
| 标准包装： | 73 |
| 系列： | PolyPhase® |
| PWM 型： | 电流模式 |
| 输出数： | 2 |
| 频率 - 最大： | 585kHz |
| 占空比： | 99.4% |
| 电源电压： | 4 V ~ 36 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 包装： | 管件 |
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LTC3826
APPLICATIONS INFORMATION
to PLLIN/MODE, is shown in Figure 9 and speci?ed in the
Electrical Characteristics table. Note that the LTC3826 can
only be synchronized to an external clock whose frequency
is within range of the LTC3826’s internal VCO, which is
nominally 115kHz to 800kHz. This is guaranteed to be
between 140kHz and 650kHz. A simpli?ed block diagram
is shown in Figure 10.
If the external clock frequency is greater than the internal
acquires lock. Typically R LP = 10k and C LP is 2200pF to
0.01μF.
Typically, the external clock (on PLLIN/MODE pin) input high
threshold is 1.6V, while the input low threshold is 1.2V.
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
Table 2
oscillator’s frequency, f OSC , then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than f OSC , current is sunk continuously, pulling down
the PLLLPF pin. If the external and internal frequencies
PLLLPF PIN
0V
Floating
INTV CC
RC Loop Filter
PLLIN/MODE PIN
DC Voltage
DC Voltage
DC Voltage
Clock Signal
FREQUENCY
250kHz
390kHz
530kHz
Phase-Locked to External Clock
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLLPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the ?lter capacitor C LP holds the voltage.
The loop ?lter components, C LP and R LP , smooth out
Minimum On-Time Considerations
Minimum on-time t ON(MIN) is the smallest time duration
that the LTC3826 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
the current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The ?lter
components C LP and R LP determine how fast the loop
900
800
700
t ON ( MIN ) <
V OUT
V IN ( f )
2.4V
R LP
C LP
600
500
PLLIN/
MODE
DIGITAL
PLLLPF
400
300
EXTERNAL
OSCILLATOR
PHASE/
FREQUENCY
DETECTOR
OSCILLATOR
200
100
0
0
0.5
1 1.5
2
2.5
3826 F10
PLLLPF VOLTAGE (V)
3826 F09
Figure 10. Phase-Locked Loop Block Diagram
Figure 9. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
3826fc
23
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