参数资料
型号: LTC3834IFE#PBF
厂商: Linear Technology
文件页数: 12/28页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 20TSSOP
标准包装: 74
PWM 型: 电流模式
输出数: 1
频率 - 最大: 580kHz
占空比: 99.4%
电源电压: 4 V ~ 36 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)裸露焊盘
包装: 管件
LTC3834
OPERATION
Frequency Selection and Phase-Locked Loop
(PLLLPF and PLLIN/MODE Pins)
The selection of switching frequency is a trade-off between
ef?ciency and component size. Low frequency opera-
tion increases ef?ciency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3834’s controllers can
be selected using the PLLLPF pin.
If the PLLIN/MODE pin is not being driven by an exter-
nal clock source, the PLLLPF pin can be ?oated, tied to
INTVCC, or tied to SGND to select 400kHz, 530kHz or
signal on the CLKOUT pin can be used to synchronize
additional power stages in a multiphase power supply
solution feeding a single, high current output or multiple
separate outputs. The PHASMD pin is used to adjust the
phase of the CLKOUT signal, as summarized in Table 1.
The phases are calculated relative to the zero degrees
phase being de?ned as the rising edge of the top gate
driver output (TG).
The CLKOUT pin has an open-drain output device. Normally,
a 10k to 100k resistor can be connected from this pin to a
voltage supply that is less than or equal to 8.5V.
Table 1
250kHz, respectively.
A phase-locked loop (PLL) is available on the LTC3834
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. In this
V PHASMD
GND
Floating
INTV CC
CLKOUT PHASE
90°
120°
180°
case, a series R-C should be connected between the PLLLPF
pin and SGND to serve as the PLL’s loop ?lter. The LTC3834
phase detector adjusts the voltage on the PLLLPF pin to
align the turn-on of the external top MOSFET to the rising
edge of the synchronizing signal.
The typical capture range of the LTC3834’s phase-locked
loop is from approximately 115kHz to 800kHz, with a
guarantee to be between 140kHz and 650kHz. In other
words, the LTC3834’s PLL is guaranteed to lock to an
external clock source whose frequency is between 140kHz
and 650kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
PolyPhase Applications (CLKOUT and PHASMD Pins)
The LTC3834 features two pins (CLKOUT and PHASMD)
that allow other controller ICs to be daisy-chained with
Output Overvoltage Protection
An overvoltage comparator guards against transient over-
shoots as well as other more serious conditions that may
overvoltage the output. When the V FB pin rises to more
than 10% higher than its regulation point of 0.800V, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Power Good (PGOOD) Pin
The PGOOD pin is connected to an open-drain of an internal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when the V FB pin voltage is not within
±10% of the 0.8V reference voltage. The PGOOD pin is also
pulled low when the RUN pin is low (shut down). When
the V FB pin voltage is within the ±10% requirement, the
MOSFET is turned off and the pin is allowed to be pulled
up by an external resistor to a source of up to 8.5V.
the LTC3834 in PolyPhase applications. The clock output
3834fb
12
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