参数资料
型号: LTC3835EFE#PBF
厂商: Linear Technology
文件页数: 8/30页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 20TSSOP
标准包装: 74
PWM 型: 电流模式,混合
输出数: 1
频率 - 最大: 580kHz
占空比: 99.4%
电源电压: 4 V ~ 36 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)裸露焊盘
包装: 管件

LTC3835
PIN FUNCTIONS
(FE Package/UFD Package)
CLKOUT (Pin 1/Pin 19): Open-Drain Output Clock Signal
available to daisychain other controller ICs for additional
MOSFET driver stages/phases.
PLLLPF (Pin 2/Pin 20): The phase-locked loop’s lowpass
filter is tied to this pin when synchronizing to an external
clock. Alternatively, tie this pin to GND, V IN or leave floating
to select 250kHz, 530kHz or 400kHz switching frequency.
I TH (Pin 3/Pin 1): Error Amplifier Outputs and Switching
Regulator Compensation Points. The current comparator
trip point increases with this control voltage.
TRACK/SS (Pin 4/Pin 2): External Tracking and Soft-Start
Input. The LTC3835 regulates the V FB voltage to the smaller
of 0.8V or the voltage on the TRACK/SS pin. A internal 1μA
pull-up current source is connected to this pin. A capacitor
to ground at this pin sets the ramp time to final regulated
output voltage. Alternatively, a resistor divider on another
voltage supply connected to this pin allows the LTC3835
output to track the other supply during startup.
V FB (Pin 5/Pin 3): Receives the remotely sensed feedback volt-
age from an external resistive divider across the output.
SGND (Pin 6, Exposed Pad Pin 21/Pin 4, Exposed Pad
Pin 21): Small Signal Ground. Must be routed separately
from high current grounds to the common (–) terminals
of the input capacitor. The exposed pad must be soldered
to the PCB for electrical contact and for rated thermal
performance.
PGND (Pin 7/Pin 5): Driver Power Ground. Connects to the
source of bottom (synchronous) N-channel MOSFET, anode
of the Schottky rectifier and the (–) terminal of C IN .
BG (Pin 8/Pin 6): High Current Gate Drive for Bottom
(Synchronous) N-Channel MOSFET. Voltage swing at this
pin is from ground to INTV CC .
INTV CC (Pin 9/Pin 7): Output of the Internal Linear Low
Dropout Regulator. The driver and control circuit are
powered from this voltage source. Must be decoupled to
power ground with a minimum of 4.7μF tantalum or other
low ESR capacitor.
EXTV CC (Pin 10/Pin 8): External Power Input to an Internal LDO
Connected to INTV CC . This LDO supplies V CC power, bypass-
ing the internal LDO powered from V IN whenever EXTV CC is
higher than 4.7V. See EXTV CC Connection in the Applications
Information section. Do not exceed 10V on this pin.
V IN (Pin 11/Pin 9): Main Supply Pin. A bypass capacitor should
be tied between this pin and the signal ground pin.
SW (Pin 12/Pin 10): Switch Node Connections to Inductor.
Voltage swing at this pin is from a Schottky diode (external)
voltage drop below ground to V IN .
TG (Pin 13/Pin 11): High Current Gate Drive for Top
N-Channel MOSFET. These are the outputs of floating drivers
with a voltage swing equal to INTV CC – 0.5V superimposed
on the switch node voltage SW.
BOOST (Pin 14/Pin 12): Bootstrapped Supply to the Top
Side Floating Driver. A capacitor is connected between the
BOOST and SW pins and a Schottky diode is tied between
the BOOST and INTV CC pins. Voltage swing at the BOOST
pin is from INTV CC to (V IN + INTV CC ).
RUN (Pin 15/Pin 13): Digital Run Control Input for
Controller. Forcing this pin below 0.7V shuts down all
controller functions, reducing the quiescent current that
the LTC3835 draws to approximately 10μA.
SENSE– (Pin 16/Pin 14): The (–) Input to the Differential
Current Comparator.
SENSE+ (Pin 17/Pin 15): The (+) Input to the Differential
Current Comparator. The I TH pin voltage and controlled
offsets between the SENSE– and SENSE+ pins in conjunc-
tion with R SENSE set the current trip threshold.
PGOOD (Pin 18/Pin 16): Open-Drain Logic Output. PGOOD
is pulled to ground when the voltage on the V FB pin is not
within ±10% of its set point.
PLLIN/MODE (Pin 19/Pin 17): External Synchronization
Input to Phase Detector and Forced Continuous Control
Input. When an external clock is applied to this pin, the
phase-locked loop will force the rising TG signal to be
synchronized with the rising edge of the external clock. In
this case, an R-C filter must be connected to the PLLLPF
pin. When not synchronizing to an external clock, this
input determines how the LTC3835 operates at light loads.
Pulling this pin below 0.7V selects Burst Mode operation.
3835fd
8
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