参数资料
型号: LTC3838EUHF#PBF
厂商: Linear Technology
文件页数: 29/54页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 38-QFN
标准包装: 52
系列: PolyPhase®
PWM 型: 电流模式
输出数: 2
频率 - 最大: 2MHz
电源电压: 4.5 V ~ 38 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 38-WFQFN 裸露焊盘
包装: 管件
LTC3838
APPLICATIONS INFORMATION
For applications where the main input power never exceeds
5.3V, tie the DRV CC1 and DRV CC2 pins to the V IN input
through a small resistor, (such as 1Ω to 2Ω) as shown
in Figure 8 to minimize the voltage drop caused by the
gate charge current. This will override the LDO and will
prevent DRV CC from dropping too low due to the dropout
voltage. Make sure the DRV CC voltage exceeds the R DS(ON)
test voltage for the external MOSFET which is typically at
4.5V for logic-level devices.
LTC3838
Generally for V IN > 6V, a UVLO can be set through monitoring
the V IN supply by using external voltage dividers at the RUN
pins from V IN to SGND. To design the voltage divider, note
that both RUN pins have two levels of threshold voltages.
The precision gate-drive-enable threshold voltage of 1.2V
can be used to set a V IN to turn on a channel’s switching.
If resistor dividers are used on both RUN pins, when V IN
is low enough and both RUN pins are pulled below the
~0.8V threshold, the part will shut down all bias of INTV CC
and DRV CC and be put in micropower shutdown mode.
The RUN pins’ bias currents depend on the RUN voltages.
DRV CC2
DRV CC1
R DRVCC
C DRVCC
C IN
V IN
The bias current changes should be taken into account
when designing the external voltage divider UVLO circuit.
An internal proportional-to-absolute-temperature (PTAT)
pull-up current source (~1.2μA at 25°C) is constantly con-
nected to this pin. When a RUN pin rises above 1.2V, the
corresponding channel’s TG and BG drives are turned on
and an additional 5μA temperature-independent pull-up
3838 F08
Figure 8. Setup for V IN ≤ 5.3V
Input Undervoltage Lockout (UVLO)
The LTC3838 has two functions that help protect the con-
troller in case of input undervoltage conditions. An internal
UVLO comparator constantly monitors the INTV CC and
DRV CC voltages to ensure that adequate voltages are pres-
ent. The comparator enables internal UVLO signal, which
locks out the switching action of both channels, until the
INTV CC and DR VCC1,2 pins are all above their respective
UVLO thresholds. The rising threshold (to release UVLO)
of the INTV CC is typically 4.2V, with 0.5V falling hysteresis
(to re-enable UVLO). The UVLO thresholds for DR VCC1,2 are
lower than that of INTV CC but higher than typical threshold
voltages of power MOSFETs, to prevent them from turning
on without sufficient gate drive voltages.
current is connected internally to the RUN pin. Pulling the
RUN pin to fall below 1.2V by more than an 80mV hyster-
esis turns off TG and BG of the corresponding channel,
and the additional 5μA pull-up current is disconnected.
As voltage on a RUN pin increases, typically beyond 3V,
its bias current will start to reverse direction and flow into
the RUN pin. Keep in mind that neither of the RUN pins
can sink more than 50μA; Even if a RUN pin may slightly
exceed 6V when sinking 50μA, a RUN pin should never
be forced to higher than 6V by a low impedance voltage
source to prevent faulty conditions.
Soft-Start and Tracking
The LTC3838 has the ability to either soft-start by itself
with a capacitor or track the output of another channel or
an external supply. Note that the soft-start and tracking
features are achieved not by limiting the maximum output
current of the controller, but by controlling the output ramp
voltage according to the ramp rate on the TRACK/SS pin.
3838fa
29
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